Refactor package hierarchy. (#25)
authorHenry Cook <henry@sifive.com>
Fri, 7 Jul 2017 17:48:57 +0000 (10:48 -0700)
committerGitHub <noreply@github.com>
Fri, 7 Jul 2017 17:48:57 +0000 (10:48 -0700)
commitfb9dd313741196a062e6a0f6462cf3a2bce710a9
treec704569bee11d11244e172d754f645f92b1bafef
parent66b2fd11bd1ec6a8a05c4929893c51c7570284fd
Refactor package hierarchy. (#25)
27 files changed:
src/main/scala/devices/gpio/GPIO.scala
src/main/scala/devices/gpio/GPIOPeriphery.scala
src/main/scala/devices/gpio/JTAG.scala
src/main/scala/devices/i2c/I2C.scala
src/main/scala/devices/i2c/I2CPeriphery.scala
src/main/scala/devices/mockaon/MockAON.scala
src/main/scala/devices/mockaon/MockAONPeriphery.scala
src/main/scala/devices/mockaon/MockAONWrapper.scala
src/main/scala/devices/mockaon/PMU.scala
src/main/scala/devices/mockaon/WatchdogTimer.scala
src/main/scala/devices/pwm/PWM.scala
src/main/scala/devices/pwm/PWMPeriphery.scala
src/main/scala/devices/spi/SPIBundle.scala
src/main/scala/devices/spi/SPIPeriphery.scala
src/main/scala/devices/spi/TLSPI.scala
src/main/scala/devices/spi/TLSPIFlash.scala
src/main/scala/devices/uart/UART.scala
src/main/scala/devices/uart/UARTPeriphery.scala
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
src/main/scala/util/RegMapFIFO.scala
src/main/scala/util/ResetCatchAndSync.scala
src/main/scala/util/Timer.scala