projects
/
sifive-blocks.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
90e6ea1
)
GPIO: IOF should not override PUE and DS
gpio_iof_pueds
author
Megan Wachs
<megan@sifive.com>
Wed, 8 Nov 2017 23:15:32 +0000
(15:15 -0800)
committer
Megan Wachs
<megan@sifive.com>
Wed, 8 Nov 2017 23:15:32 +0000
(15:15 -0800)
src/main/scala/devices/gpio/GPIO.scala
patch
|
blob
|
history
diff --git
a/src/main/scala/devices/gpio/GPIO.scala
b/src/main/scala/devices/gpio/GPIO.scala
index f598dbb00c0dac677202f160b8638e1dd9f85ee1..f5098cf384d69259089ccdb9dfee6a0cc6e4c3e7 100644
(file)
--- a/
src/main/scala/devices/gpio/GPIO.scala
+++ b/
src/main/scala/devices/gpio/GPIO.scala
@@
-168,10
+168,10
@@
trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
// This strips off the valid.
val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
// This strips off the valid.
- val iof0Ctrl = Wire(Vec(c.width, new
EnhancedPin
Ctrl()))
- val iof1Ctrl = Wire(Vec(c.width, new
EnhancedPin
Ctrl()))
+ val iof0Ctrl = Wire(Vec(c.width, new
IOF
Ctrl()))
+ val iof1Ctrl = Wire(Vec(c.width, new
IOF
Ctrl()))
- val iofCtrl = Wire(Vec(c.width, new
EnhancedPin
Ctrl()))
+ val iofCtrl = Wire(Vec(c.width, new
IOF
Ctrl()))
val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
for (pin <- 0 until c.width) {
val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
for (pin <- 0 until c.width) {