From: Megan Wachs Date: Fri, 31 Mar 2017 03:01:30 +0000 (-0700) Subject: Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=1af6ce1c85b189982e970c088405c9117f5fbb9d;hp=6a3b5e1a31f0fa317d9ede581545ba27952ab1a4 Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD --- diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala index 8734539..ba40bc6 100644 --- a/src/main/scala/devices/gpio/JTAG.scala +++ b/src/main/scala/devices/gpio/JTAG.scala @@ -11,33 +11,31 @@ import Chisel._ // ------------------------------------------------------------ import config._ -import junctions.{JTAGIO} +import jtag.{JTAGIO} -class JTAGPinsIO extends Bundle { +class JTAGPinsIO(hasTRSTn: Boolean = true) extends Bundle { val TCK = new GPIOPin() val TMS = new GPIOPin() val TDI = new GPIOPin() val TDO = new GPIOPin() - val TRST_n = new GPIOPin() + val TRSTn = if (hasTRSTn) Option(new GPIOPin()) else None } -class JTAGGPIOPort(drvTdo: Boolean = false)(implicit p: Parameters) extends Module { +class JTAGGPIOPort(hasTRSTn: Boolean = true)(implicit p: Parameters) extends Module { val io = new Bundle { - val jtag = new JTAGIO(drvTdo) - val pins = new JTAGPinsIO() + // TODO: make this not hard-coded true. + val jtag = new JTAGIO(hasTRSTn) + val pins = new JTAGPinsIO(hasTRSTn) } io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true)) io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true)) - io.jtag.TRST := ~GPIOInputPinCtrl(io.pins.TRST_n, pue = Bool(true)) - - GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO) - if (drvTdo) { - io.pins.TDO.o.oe := io.jtag.DRV_TDO.get - } + io.jtag.TRSTn.foreach{t => t := GPIOInputPinCtrl(io.pins.TRSTn.get, pue = Bool(true))} + GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data) + io.pins.TDO.o.oe := io.jtag.TDO.driven }