From: Wesley W. Terpstra Date: Wed, 27 Sep 2017 23:33:18 +0000 (-0700) Subject: diplomacy: update to new API (#40) X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985 diplomacy: update to new API (#40) --- diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala index d4cd24e..f598dbb 100644 --- a/src/main/scala/devices/gpio/GPIO.scala +++ b/src/main/scala/devices/gpio/GPIO.scala @@ -2,6 +2,7 @@ package sifive.blocks.devices.gpio import Chisel._ +import chisel3.experimental.MultiIOModule import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl} import freechips.rocketchip.config.Parameters import freechips.rocketchip.util.SynchronizerShiftReg @@ -87,7 +88,7 @@ trait HasGPIOBundleContents extends Bundle { val port = new GPIOPortIO(params) } -trait HasGPIOModuleContents extends Module with HasRegMap { +trait HasGPIOModuleContents extends MultiIOModule with HasRegMap { val io: HasGPIOBundleContents val params: GPIOParams val c = params diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala index d3b9cf5..149f707 100644 --- a/src/main/scala/devices/gpio/GPIOPeriphery.scala +++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala @@ -4,7 +4,7 @@ package sifive.blocks.devices.gpio import Chisel._ import freechips.rocketchip.config.Field import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp} import freechips.rocketchip.util.HeterogeneousBag case object PeripheryGPIOKey extends Field[Seq[GPIOParams]] @@ -23,7 +23,7 @@ trait HasPeripheryGPIOBundle { val gpio: HeterogeneousBag[GPIOPortIO] } -trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGPIOBundle { +trait HasPeripheryGPIOModuleImp extends LazyModuleImp with HasPeripheryGPIOBundle { val outer: HasPeripheryGPIO val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))) diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala index 147a739..aecf2dc 100644 --- a/src/main/scala/devices/i2c/I2C.scala +++ b/src/main/scala/devices/i2c/I2C.scala @@ -42,6 +42,7 @@ package sifive.blocks.devices.i2c import Chisel._ +import chisel3.experimental.MultiIOModule import freechips.rocketchip.config._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ @@ -64,7 +65,7 @@ trait HasI2CBundleContents extends Bundle { val port = new I2CPort } -trait HasI2CModuleContents extends Module with HasRegMap { +trait HasI2CModuleContents extends MultiIOModule with HasRegMap { val io: HasI2CBundleContents val params: I2CParams diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala index f439407..d4ad9fe 100644 --- a/src/main/scala/devices/i2c/I2CPeriphery.scala +++ b/src/main/scala/devices/i2c/I2CPeriphery.scala @@ -4,7 +4,7 @@ package sifive.blocks.devices.i2c import Chisel._ import freechips.rocketchip.config.Field import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} case object PeripheryI2CKey extends Field[Seq[I2CParams]] @@ -22,7 +22,7 @@ trait HasPeripheryI2CBundle { val i2c: Vec[I2CPort] } -trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle { +trait HasPeripheryI2CModuleImp extends LazyModuleImp with HasPeripheryI2CBundle { val outer: HasPeripheryI2C val i2c = IO(Vec(outer.i2cParams.size, new I2CPort)) diff --git a/src/main/scala/devices/mockaon/MockAON.scala b/src/main/scala/devices/mockaon/MockAON.scala index c6a7fb6..0606822 100644 --- a/src/main/scala/devices/mockaon/MockAON.scala +++ b/src/main/scala/devices/mockaon/MockAON.scala @@ -2,6 +2,7 @@ package sifive.blocks.devices.mockaon import Chisel._ +import chisel3.experimental.MultiIOModule import freechips.rocketchip.config.Parameters import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ @@ -49,7 +50,7 @@ trait HasMockAONBundleContents extends Bundle { val resetCauses = new ResetCauses().asInput } -trait HasMockAONModuleContents extends Module with HasRegMap { +trait HasMockAONModuleContents extends MultiIOModule with HasRegMap { val io: HasMockAONBundleContents val params: MockAONParams val c = params diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala index b20bee2..8de7ad9 100644 --- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala +++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.util.SynchronizerShiftReg import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} import freechips.rocketchip.devices.debug.HasPeripheryDebug import freechips.rocketchip.devices.tilelink.HasPeripheryClint -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource} import freechips.rocketchip.util.ResetCatchAndSync @@ -32,7 +32,7 @@ trait HasPeripheryMockAONBundle { } } -trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripheryMockAONBundle { +trait HasPeripheryMockAONModuleImp extends LazyModuleImp with HasPeripheryMockAONBundle { val outer: HasPeripheryMockAON val aon = IO(new MockAONWrapperBundle) diff --git a/src/main/scala/devices/mockaon/MockAONWrapper.scala b/src/main/scala/devices/mockaon/MockAONWrapper.scala index 9ac4308..bfc73b2 100644 --- a/src/main/scala/devices/mockaon/MockAONWrapper.scala +++ b/src/main/scala/devices/mockaon/MockAONWrapper.scala @@ -30,8 +30,6 @@ class MockAONWrapperBundle extends Bundle { class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends LazyModule { - val node = TLAsyncInputNode() - val intnode = IntOutputNode() val aon = LazyModule(new TLMockAON(w, c)) // We only need to isolate the signals @@ -45,20 +43,18 @@ class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends L val isolation = LazyModule(new TLIsolation(fOut = isoOut, fIn = isoIn)) val crossing = LazyModule(new TLAsyncCrossingSink(depth = 1)) - isolation.node := node + val node: TLAsyncInwardNode = isolation.node crossing.node := isolation.node - val crossing_monitor = (aon.node := crossing.node) + aon.node := crossing.node // crossing lives outside in Periphery - intnode := aon.intnode + val intnode: IntOutwardNode = aon.intnode lazy val module = new LazyModuleImp(this) { - val io = new MockAONWrapperBundle { - val in = node.bundleIn - val ip = intnode.bundleOut + val io = IO(new MockAONWrapperBundle { val rtc = Clock(OUTPUT) val ndreset = Bool(INPUT) - } + }) val aon_io = aon.module.io val pins = io.pins @@ -122,11 +118,6 @@ class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends L crossing.module.clock := lfclk crossing.module.reset := crossing_slave_reset - crossing_monitor.foreach { lm => - lm.module.clock := lfclk - lm.module.reset := crossing_slave_reset - } - // Note that aon.moff.corerst is synchronous // to aon.module.clock, so this is safe. isolation.module.io.iso_out := aon.module.io.moff.corerst diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala index 3d35d81..6381004 100644 --- a/src/main/scala/devices/pwm/PWM.scala +++ b/src/main/scala/devices/pwm/PWM.scala @@ -2,6 +2,7 @@ package sifive.blocks.devices.pwm import Chisel._ +import chisel3.experimental.MultiIOModule import Chisel.ImplicitConversions._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.regmapper._ @@ -48,7 +49,7 @@ trait HasPWMBundleContents extends Bundle { val gpio = Vec(params.ncmp, Bool()).asOutput } -trait HasPWMModuleContents extends Module with HasRegMap { +trait HasPWMModuleContents extends MultiIOModule with HasRegMap { val io: HasPWMBundleContents val params: PWMParams diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala index d3e1c5b..00043ab 100644 --- a/src/main/scala/devices/pwm/PWMPeriphery.scala +++ b/src/main/scala/devices/pwm/PWMPeriphery.scala @@ -4,7 +4,7 @@ package sifive.blocks.devices.pwm import Chisel._ import freechips.rocketchip.config.Field import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import freechips.rocketchip.util.HeterogeneousBag import sifive.blocks.devices.pinctrl.{Pin} @@ -31,7 +31,7 @@ trait HasPeripheryPWMBundle { } -trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle { +trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle { val outer: HasPeripheryPWM val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))) diff --git a/src/main/scala/devices/pwm/PWMPins.scala b/src/main/scala/devices/pwm/PWMPins.scala index 7ab76f0..03acc90 100644 --- a/src/main/scala/devices/pwm/PWMPins.scala +++ b/src/main/scala/devices/pwm/PWMPins.scala @@ -4,7 +4,7 @@ package sifive.blocks.devices.pwm import Chisel._ import freechips.rocketchip.config.Field import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import freechips.rocketchip.util.HeterogeneousBag import sifive.blocks.devices.pinctrl.{Pin} diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index 595ffc3..b2edb0f 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -4,7 +4,7 @@ package sifive.blocks.devices.spi import Chisel._ import freechips.rocketchip.config.Field import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp,BufferParams} +import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams} import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer} import freechips.rocketchip.util.HeterogeneousBag @@ -25,7 +25,7 @@ trait HasPeripherySPIBundle { } -trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle { +trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle { val outer: HasPeripherySPI val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))) @@ -55,7 +55,7 @@ trait HasPeripherySPIFlashBundle { } -trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle { +trait HasPeripherySPIFlashModuleImp extends LazyModuleImp with HasPeripherySPIFlashBundle { val outer: HasPeripherySPIFlash val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_)))) diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala index 0af8e35..ea28f89 100644 --- a/src/main/scala/devices/spi/TLSPI.scala +++ b/src/main/scala/devices/spi/TLSPI.scala @@ -47,15 +47,12 @@ case class SPIParams( require(sampleDelay >= 0) } -class SPITopBundle(val i: HeterogeneousBag[Vec[Bool]], val r: HeterogeneousBag[TLBundle]) extends Bundle - -class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase) +class SPITopModule(c: SPIParamsBase, outer: TLSPIBase) extends LazyModuleImp(outer) { - val io = new Bundle { + val io = IO(new Bundle { val port = new SPIPortIO(c) - val tl = bundle - } + }) val ctrl = Reg(init = SPIControl.init(c)) @@ -72,7 +69,8 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS val ie = Reg(init = new SPIInterrupts().fromBits(Bits(0))) val ip = fifo.io.ip - io.tl.i(0)(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm) + val (io_int, _) = outer.intnode.out(0) + io_int(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm) protected val regmapBase = Seq( SPICRs.sckdiv -> Seq(RegField(c.divisorBits, ctrl.sck.div)), @@ -115,7 +113,7 @@ abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) exten } class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) { - lazy val module = new SPITopModule(c, new SPITopBundle(intnode.bundleOut, rnode.bundleIn), this) { + lazy val module = new SPITopModule(c, this) { mac.io.link <> fifo.io.link rnode.regmap(regmapBase:_*) } diff --git a/src/main/scala/devices/spi/TLSPIFlash.scala b/src/main/scala/devices/spi/TLSPIFlash.scala index e433fec..a66ca1c 100644 --- a/src/main/scala/devices/spi/TLSPIFlash.scala +++ b/src/main/scala/devices/spi/TLSPIFlash.scala @@ -41,16 +41,13 @@ case class SPIFlashParams( require(sampleDelay >= 0) } -class SPIFlashTopBundle(i: HeterogeneousBag[Vec[Bool]], r: HeterogeneousBag[TLBundle], val f: HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r) - -class SPIFlashTopModule[B <: SPIFlashTopBundle] - (c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase) - extends SPITopModule(c, bundle, outer) { +class SPIFlashTopModule(c: SPIFlashParamsBase, outer: TLSPIFlashBase) + extends SPITopModule(c, outer) { val flash = Module(new SPIFlashMap(c)) val arb = Module(new SPIArbiter(c, 2)) - private val f = io.tl.f.head + private val (f, _) = outer.fnode.in(0) // Tie unused channels f.b.valid := Bool(false) f.c.ready := Bool(true) @@ -68,7 +65,7 @@ class SPIFlashTopModule[B <: SPIFlashTopBundle] flash.io.addr.valid := f.a.valid f.a.ready := flash.io.addr.ready - f.d.bits := outer.fnode.edgesIn.head.AccessAck(a, flash.io.data.bits) + f.d.bits := outer.fnode.edges.in.head.AccessAck(a, flash.io.data.bits) f.d.valid := flash.io.data.valid flash.io.data.ready := f.d.ready @@ -96,18 +93,19 @@ class SPIFlashTopModule[B <: SPIFlashTopBundle] abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Parameters) extends TLSPIBase(w,c)(p) { require(isPow2(c.fSize)) - val fnode = TLManagerNode(1, TLManagerParameters( - address = Seq(AddressSet(c.fAddress, c.fSize-1)), - resources = device.reg("mem"), - regionType = RegionType.UNCACHED, - executable = true, - supportsGet = TransferSizes(1, 1), - fifoId = Some(0))) + val fnode = TLManagerNode(Seq(TLManagerPortParameters( + managers = Seq(TLManagerParameters( + address = Seq(AddressSet(c.fAddress, c.fSize-1)), + resources = device.reg("mem"), + regionType = RegionType.UNCACHED, + executable = true, + supportsGet = TransferSizes(1, 1), + fifoId = Some(0))), + beatBytes = 1))) } class TLSPIFlash(w: Int, c: SPIFlashParams)(implicit p: Parameters) extends TLSPIFlashBase(w,c)(p) { - lazy val module = new SPIFlashTopModule(c, - new SPIFlashTopBundle(intnode.bundleOut, rnode.bundleIn, fnode.bundleIn), this) { + lazy val module = new SPIFlashTopModule(c, this) { arb.io.inner(0) <> flash.io.link arb.io.inner(1) <> fifo.io.link diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala index de2cf55..449f897 100644 --- a/src/main/scala/devices/uart/UART.scala +++ b/src/main/scala/devices/uart/UART.scala @@ -2,6 +2,7 @@ package sifive.blocks.devices.uart import Chisel._ +import chisel3.experimental.MultiIOModule import freechips.rocketchip.config.Parameters import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ @@ -198,7 +199,7 @@ class UARTInterrupts extends Bundle { val txwm = Bool() } -trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasRegMap { +trait HasUARTTopModuleContents extends MultiIOModule with HasUARTParameters with HasRegMap { val io: HasUARTTopBundleContents implicit val p: Parameters def params: UARTParams diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index 95d0c3b..d1db77b 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -5,7 +5,7 @@ import Chisel._ import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.config.Field import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} case object PeripheryUARTKey extends Field[Seq[UARTParams]] @@ -29,7 +29,7 @@ trait HasPeripheryUARTBundle { } -trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle { +trait HasPeripheryUARTModuleImp extends LazyModuleImp with HasPeripheryUARTBundle { val outer: HasPeripheryUART val uart = IO(Vec(outer.uartParams.size, new UARTPortIO)) diff --git a/src/main/scala/devices/uart/UARTPins.scala b/src/main/scala/devices/uart/UARTPins.scala index e04fdf3..4201f90 100644 --- a/src/main/scala/devices/uart/UARTPins.scala +++ b/src/main/scala/devices/uart/UARTPins.scala @@ -6,7 +6,7 @@ import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.config.Field import freechips.rocketchip.util.SyncResetSynchronizerShiftReg import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import sifive.blocks.devices.pinctrl.{Pin} class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {