From: Megan Wachs <megan@sifive.com>
Date: Fri, 7 Apr 2017 23:42:32 +0000 (-0700)
Subject: MockAON: Accept the non-debug interrupt as an input to overall reset.
X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=9ba47b76c6e36df9d8402b829fd5002489ebf476

MockAON: Accept the non-debug interrupt as an input to overall reset.
---

diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
index ef82dde..1f99c31 100644
--- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala
+++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
@@ -44,4 +44,5 @@ trait HasPeripheryMockAONModule extends HasTopLevelNetworksModule {
 
   outer.coreplex.module.io.rtcToggle := outer.aon.module.io.rtc.asUInt.toBool
 
+  outer.aon.module.io.ndreset := outer.coreplex.module.io.ndreset
 }
diff --git a/src/main/scala/devices/mockaon/MockAONWrapper.scala b/src/main/scala/devices/mockaon/MockAONWrapper.scala
index d472ddd..099dba7 100644
--- a/src/main/scala/devices/mockaon/MockAONWrapper.scala
+++ b/src/main/scala/devices/mockaon/MockAONWrapper.scala
@@ -56,6 +56,7 @@ class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends L
       val in = node.bundleIn
       val ip = intnode.bundleOut
       val rtc  = Clock(OUTPUT)
+      val ndreset = Bool(INPUT)
     }
 
     val aon_io = aon.module.io
@@ -99,7 +100,7 @@ class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends L
     val lfclk = aon_io.lfclk
 
     val aonrst_catch = Module (new ResetCatchAndSync(3))
-    aonrst_catch.reset := erst | aon_io.wdog_rst
+    aonrst_catch.reset := erst | aon_io.wdog_rst | io.ndreset
     aonrst_catch.clock := lfclk
     aon.module.reset := aonrst_catch.io.sync_reset