From: Megan Wachs <megan@sifive.com>
Date: Tue, 13 Jun 2017 01:08:35 +0000 (-0700)
Subject: UART: actually return the pins, not just the module. We should do this for the other... 
X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=b3f656affe1344320523311c7ca8db64342bda5c

UART: actually return the pins, not just the module. We should do this for the other peripherals as well
---

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 1f8011e..58b1c9e 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -29,10 +29,10 @@ trait HasPeripheryUARTBundle {
     uarts.foreach { _.rxd := UInt(1) }
   }
 
-  def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u =>
+  def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
     val pin = Module(new UARTGPIOPort(syncStages))
     pin.io.uart <> u
-    pin
+    pin.io.pins
   }
 }