From: Yunsup Lee <yunsup@sifive.com>
Date: Tue, 2 May 2017 21:36:39 +0000 (-0700)
Subject: Merge pull request #11 from sifive/spi
X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=fd894746218c0c4e036a2d999587723d1dbfa9ed;hp=6eddf517a38156a22b9b831ba92626673a11d603

Merge pull request #11 from sifive/spi

SPI errata fixes
---

diff --git a/src/main/scala/devices/spi/SPIFIFO.scala b/src/main/scala/devices/spi/SPIFIFO.scala
index a322a1b..5bc6e82 100644
--- a/src/main/scala/devices/spi/SPIFIFO.scala
+++ b/src/main/scala/devices/spi/SPIFIFO.scala
@@ -41,7 +41,7 @@ class SPIFIFO(c: SPIParamsBase) extends Module {
 
   val proto = SPIProtocol.decode(io.link.fmt.proto).zipWithIndex
   val cnt_quot = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len >> i) })
-  val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len(i, 0).orR) })
+  val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (if (i > 0) io.ctrl.fmt.len(i-1, 0).orR else UInt(0)) })
   io.link.fmt <> io.ctrl.fmt
   io.link.cnt := cnt_quot + cnt_rmdr
 
diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala
index 802233d..a9ce076 100644
--- a/src/main/scala/devices/spi/SPIPhysical.scala
+++ b/src/main/scala/devices/spi/SPIPhysical.scala
@@ -82,7 +82,7 @@ class SPIPhysical(c: SPIParamsBase) extends Module {
   }
 
   val tx = (ctrl.fmt.iodir === SPIDirection.Tx)
-  val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _)
+  val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _).init
   val txen = txen_in :+ txen_in.last
 
   io.port.sck := sck