From: Henry Cook Date: Wed, 5 Jul 2017 18:53:56 +0000 (-0700) Subject: Refactor package hierarchy. X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=refs%2Fheads%2Ffreechips-packages Refactor package hierarchy. --- diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala index 12ac055..ae468ce 100644 --- a/src/main/scala/devices/gpio/GPIO.scala +++ b/src/main/scala/devices/gpio/GPIO.scala @@ -2,10 +2,10 @@ package sifive.blocks.devices.gpio import Chisel._ -import config.Parameters -import regmapper._ -import uncore.tilelink2._ -import util.{AsyncResetRegVec, GenericParameterizedBundle} +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle} case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false) diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala index b7a479c..204f767 100644 --- a/src/main/scala/devices/gpio/GPIOPeriphery.scala +++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala @@ -2,11 +2,11 @@ package sifive.blocks.devices.gpio import Chisel._ -import config.Field -import diplomacy.{LazyModule,LazyMultiIOModuleImp} -import rocketchip.HasSystemNetworks -import uncore.tilelink2.TLFragmenter -import util.HeterogeneousBag +import freechips.rocketchip.config.Field +import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} +import freechips.rocketchip.chip.HasSystemNetworks +import freechips.rocketchip.tilelink.TLFragmenter +import freechips.rocketchip.util.HeterogeneousBag case object PeripheryGPIOKey extends Field[Seq[GPIOParams]] diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala index ba40bc6..63d9cc2 100644 --- a/src/main/scala/devices/gpio/JTAG.scala +++ b/src/main/scala/devices/gpio/JTAG.scala @@ -10,8 +10,8 @@ import Chisel._ // to put them otherwise. // ------------------------------------------------------------ -import config._ -import jtag.{JTAGIO} +import freechips.rocketchip.config._ +import freechips.rocketchip.jtag.{JTAGIO} class JTAGPinsIO(hasTRSTn: Boolean = true) extends Bundle { diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala index f0df22a..58ad548 100644 --- a/src/main/scala/devices/i2c/I2C.scala +++ b/src/main/scala/devices/i2c/I2C.scala @@ -42,10 +42,10 @@ package sifive.blocks.devices.i2c import Chisel._ -import config._ -import regmapper._ -import uncore.tilelink2._ -import util.{AsyncResetRegVec, Majority} +import freechips.rocketchip.config._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.{AsyncResetRegVec, Majority} import sifive.blocks.devices.gpio.{GPIOPinCtrl} case class I2CParams(address: BigInt) diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala index fc62c6b..94bbadd 100644 --- a/src/main/scala/devices/i2c/I2CPeriphery.scala +++ b/src/main/scala/devices/i2c/I2CPeriphery.scala @@ -2,10 +2,10 @@ package sifive.blocks.devices.i2c import Chisel._ -import config.Field -import diplomacy.{LazyModule,LazyMultiIOModuleImp} -import rocketchip.{HasSystemNetworks} -import uncore.tilelink2.TLFragmenter +import freechips.rocketchip.config.Field +import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} +import freechips.rocketchip.chip.{HasSystemNetworks} +import freechips.rocketchip.tilelink.TLFragmenter case object PeripheryI2CKey extends Field[Seq[I2CParams]] diff --git a/src/main/scala/devices/mockaon/MockAON.scala b/src/main/scala/devices/mockaon/MockAON.scala index f5ef203..c6a7fb6 100644 --- a/src/main/scala/devices/mockaon/MockAON.scala +++ b/src/main/scala/devices/mockaon/MockAON.scala @@ -2,9 +2,9 @@ package sifive.blocks.devices.mockaon import Chisel._ -import config._ -import regmapper._ -import uncore.tilelink2._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ import sifive.blocks.util.GenericTimer diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala index 91fa4fb..240f89b 100644 --- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala +++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala @@ -2,11 +2,11 @@ package sifive.blocks.devices.mockaon import Chisel._ -import config.Field -import diplomacy.{LazyModule, LazyMultiIOModuleImp} -import rocketchip.{HasSystemNetworks, HasCoreplexRISCVPlatform} -import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter} -import util.ResetCatchAndSync +import freechips.rocketchip.config.Field +import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.chip.{HasSystemNetworks, HasCoreplexRISCVPlatform} +import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource, TLFragmenter} +import freechips.rocketchip.util.ResetCatchAndSync case object PeripheryMockAONKey extends Field[MockAONParams] diff --git a/src/main/scala/devices/mockaon/MockAONWrapper.scala b/src/main/scala/devices/mockaon/MockAONWrapper.scala index 099dba7..9062ff7 100644 --- a/src/main/scala/devices/mockaon/MockAONWrapper.scala +++ b/src/main/scala/devices/mockaon/MockAONWrapper.scala @@ -2,12 +2,13 @@ package sifive.blocks.devices.mockaon import Chisel._ -import config._ -import diplomacy._ -import uncore.tilelink2._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util._ import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl} import sifive.blocks.util.{DeglitchShiftRegister, ResetCatchAndSync} -import util._ + /* The wrapper handles the Clock and Reset Generation for The AON block itself, and instantiates real pad controls (aka pull-ups)*/ diff --git a/src/main/scala/devices/mockaon/PMU.scala b/src/main/scala/devices/mockaon/PMU.scala index 2c7964a..2020db7 100644 --- a/src/main/scala/devices/mockaon/PMU.scala +++ b/src/main/scala/devices/mockaon/PMU.scala @@ -3,7 +3,7 @@ package sifive.blocks.devices.mockaon import Chisel._ import Chisel.ImplicitConversions._ -import util._ +import freechips.rocketchip.util._ import sifive.blocks.util.SRLatch import sifive.blocks.util.{SlaveRegIF} diff --git a/src/main/scala/devices/mockaon/WatchdogTimer.scala b/src/main/scala/devices/mockaon/WatchdogTimer.scala index 5383dbe..390dc55 100644 --- a/src/main/scala/devices/mockaon/WatchdogTimer.scala +++ b/src/main/scala/devices/mockaon/WatchdogTimer.scala @@ -3,7 +3,7 @@ package sifive.blocks.devices.mockaon import Chisel._ import Chisel.ImplicitConversions._ -import util.AsyncResetReg +import freechips.rocketchip.util.AsyncResetReg import sifive.blocks.util.{SlaveRegIF, GenericTimer} diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala index 14f365d..044d1bd 100644 --- a/src/main/scala/devices/pwm/PWM.scala +++ b/src/main/scala/devices/pwm/PWM.scala @@ -3,11 +3,10 @@ package sifive.blocks.devices.pwm import Chisel._ import Chisel.ImplicitConversions._ -import config.Parameters -import regmapper._ -import uncore.tilelink2._ -import util._ - +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util._ import sifive.blocks.util.GenericTimer // Core PWM Functionality & Register Interface diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala index d22de54..ea17f8a 100644 --- a/src/main/scala/devices/pwm/PWMPeriphery.scala +++ b/src/main/scala/devices/pwm/PWMPeriphery.scala @@ -2,11 +2,11 @@ package sifive.blocks.devices.pwm import Chisel._ -import config.Field -import diplomacy.{LazyModule,LazyMultiIOModuleImp} -import rocketchip.HasSystemNetworks -import uncore.tilelink2.TLFragmenter -import util.HeterogeneousBag +import freechips.rocketchip.config.Field +import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} +import freechips.rocketchip.chip.HasSystemNetworks +import freechips.rocketchip.tilelink.TLFragmenter +import freechips.rocketchip.util.HeterogeneousBag import sifive.blocks.devices.gpio._ diff --git a/src/main/scala/devices/spi/SPIBundle.scala b/src/main/scala/devices/spi/SPIBundle.scala index cb96df5..332edff 100644 --- a/src/main/scala/devices/spi/SPIBundle.scala +++ b/src/main/scala/devices/spi/SPIBundle.scala @@ -2,7 +2,7 @@ package sifive.blocks.devices.spi import Chisel._ -import util.GenericParameterizedBundle +import freechips.rocketchip.util.GenericParameterizedBundle abstract class SPIBundle(val c: SPIParamsBase) extends GenericParameterizedBundle(c) { override def cloneType: SPIBundle.this.type = diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index 83e6664..15e28fa 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -2,11 +2,11 @@ package sifive.blocks.devices.spi import Chisel._ -import config.Field -import diplomacy.{LazyModule,LazyMultiIOModuleImp} -import rocketchip.HasSystemNetworks -import uncore.tilelink2.{TLFragmenter,TLWidthWidget} -import util.HeterogeneousBag +import freechips.rocketchip.config.Field +import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} +import freechips.rocketchip.chip.HasSystemNetworks +import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget} +import freechips.rocketchip.util.HeterogeneousBag case object PeripherySPIKey extends Field[Seq[SPIParams]] diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala index 5c5b9bf..0af8e35 100644 --- a/src/main/scala/devices/spi/TLSPI.scala +++ b/src/main/scala/devices/spi/TLSPI.scala @@ -2,11 +2,11 @@ package sifive.blocks.devices.spi import Chisel._ -import config._ -import diplomacy._ -import regmapper._ -import uncore.tilelink2._ - +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.HeterogeneousBag import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue} trait SPIParamsBase { @@ -47,7 +47,7 @@ case class SPIParams( require(sampleDelay >= 0) } -class SPITopBundle(val i: util.HeterogeneousBag[Vec[Bool]], val r: util.HeterogeneousBag[TLBundle]) extends Bundle +class SPITopBundle(val i: HeterogeneousBag[Vec[Bool]], val r: HeterogeneousBag[TLBundle]) extends Bundle class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase) extends LazyModuleImp(outer) { diff --git a/src/main/scala/devices/spi/TLSPIFlash.scala b/src/main/scala/devices/spi/TLSPIFlash.scala index 8968c69..1ded823 100644 --- a/src/main/scala/devices/spi/TLSPIFlash.scala +++ b/src/main/scala/devices/spi/TLSPIFlash.scala @@ -2,10 +2,11 @@ package sifive.blocks.devices.spi import Chisel._ -import config._ -import diplomacy._ -import regmapper._ -import uncore.tilelink2._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.HeterogeneousBag trait SPIFlashParamsBase extends SPIParamsBase { val fAddress: BigInt @@ -38,7 +39,7 @@ case class SPIFlashParams( require(sampleDelay >= 0) } -class SPIFlashTopBundle(i: util.HeterogeneousBag[Vec[Bool]], r: util.HeterogeneousBag[TLBundle], val f: util.HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r) +class SPIFlashTopBundle(i: HeterogeneousBag[Vec[Bool]], r: HeterogeneousBag[TLBundle], val f: HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r) class SPIFlashTopModule[B <: SPIFlashTopBundle] (c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase) diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala index e6349f1..5732fd9 100644 --- a/src/main/scala/devices/uart/UART.scala +++ b/src/main/scala/devices/uart/UART.scala @@ -2,10 +2,12 @@ package sifive.blocks.devices.uart import Chisel._ -import config._ -import regmapper._ -import uncore.tilelink2._ -import util._ +import freechips.rocketchip.chip.RTCPeriod +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy.DTSTimebase +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util._ import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue} @@ -203,7 +205,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg val rxm = Module(new UARTRx(params)) val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries)) - val divinit = p(diplomacy.DTSTimebase) * p(rocketchip.RTCPeriod) / 115200 + val divinit = p(DTSTimebase) * p(RTCPeriod) / 115200 val div = Reg(init = UInt(divinit, uartDivisorBits)) private val stopCountBits = log2Up(uartStopBits) diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index e01eb9f..b070a42 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -2,11 +2,10 @@ package sifive.blocks.devices.uart import Chisel._ -import config.Field -import diplomacy.{LazyModule, LazyMultiIOModuleImp} -import rocketchip.HasSystemNetworks -import uncore.tilelink2.TLFragmenter - +import freechips.rocketchip.config.Field +import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.chip.HasSystemNetworks +import freechips.rocketchip.tilelink.TLFragmenter import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl} import sifive.blocks.util.ShiftRegisterInit diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala index 3bb5289..9567f56 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala @@ -3,11 +3,12 @@ package sifive.blocks.devices.xilinxvc707mig import Chisel._ import chisel3.experimental.{Analog,attach} -import config._ -import diplomacy._ -import uncore.tilelink2._ -import uncore.axi4._ -import rocketchip._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.chip._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.coreplex.CacheBlockBytes +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig} trait HasXilinxVC707MIGParameters { @@ -34,7 +35,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC val xing = LazyModule(new TLAsyncCrossing) val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1)) val indexer = LazyModule(new AXI4IdIndexer(idBits = 4)) - val deint = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes))) + val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes))) val yank = LazyModule(new AXI4UserYanker) val buffer = LazyModule(new AXI4Buffer) diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala index bf187ff..540821e 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala @@ -2,8 +2,8 @@ package sifive.blocks.devices.xilinxvc707mig import Chisel._ -import diplomacy.{LazyModule, LazyMultiIOModuleImp} -import rocketchip.HasSystemNetworks +import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.chip.HasSystemNetworks trait HasPeripheryXilinxVC707MIG extends HasSystemNetworks { val module: HasPeripheryXilinxVC707MIGModuleImp diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala index 76239cf..cf8eae7 100644 --- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala +++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala @@ -2,11 +2,11 @@ package sifive.blocks.devices.xilinxvc707pciex1 import Chisel._ -import config._ -import diplomacy._ -import uncore.tilelink2._ -import uncore.axi4._ -import rocketchip._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.coreplex.CacheBlockBytes +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ import sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial} import sifive.blocks.ip.xilinx.ibufds_gte2.IBUFDS_GTE2 @@ -30,7 +30,7 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule { axi_to_pcie_x1.slave := AXI4Buffer()( AXI4UserYanker()( - AXI4Deinterleaver(p(coreplex.CacheBlockBytes))( + AXI4Deinterleaver(p(CacheBlockBytes))( AXI4IdIndexer(idBits=4)( TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))( TLAsyncCrossingSink()( @@ -40,7 +40,7 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule { AXI4Buffer()( AXI4UserYanker(capMaxFlight = Some(2))( TLToAXI4(beatBytes=4)( - TLFragmenter(4, p(coreplex.CacheBlockBytes))( + TLFragmenter(4, p(CacheBlockBytes))( TLAsyncCrossingSink()( control))))) diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala index 2a4389a..008556a 100644 --- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala +++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala @@ -2,9 +2,9 @@ package sifive.blocks.devices.xilinxvc707pciex1 import Chisel._ -import diplomacy.{LazyModule, LazyMultiIOModuleImp} -import rocketchip.HasSystemNetworks -import uncore.tilelink2._ +import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.chip.HasSystemNetworks +import freechips.rocketchip.tilelink._ trait HasPeripheryXilinxVC707PCIeX1 extends HasSystemNetworks { val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala index c7206e4..7e732f8 100644 --- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala @@ -2,11 +2,10 @@ package sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1 import Chisel._ -import config._ -import diplomacy._ -import uncore.axi4._ -import uncore.tilelink2.{IntSourceNode, IntSourcePortSimple} -import junctions._ +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple} // IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0 // Black Box diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala index d7b522f..1e01748 100644 --- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala +++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala @@ -3,8 +3,7 @@ package sifive.blocks.ip.xilinx.vc707mig import Chisel._ import chisel3.experimental.{Analog,attach} -import config._ -import junctions._ +import freechips.rocketchip.config._ // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0 // Black Box diff --git a/src/main/scala/util/RegMapFIFO.scala b/src/main/scala/util/RegMapFIFO.scala index 3e45482..698d858 100644 --- a/src/main/scala/util/RegMapFIFO.scala +++ b/src/main/scala/util/RegMapFIFO.scala @@ -2,7 +2,7 @@ package sifive.blocks.util import Chisel._ -import regmapper._ +import freechips.rocketchip.regmapper._ // MSB indicates full status object NonBlockingEnqueue { diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala index cc35686..6b483e5 100644 --- a/src/main/scala/util/ResetCatchAndSync.scala +++ b/src/main/scala/util/ResetCatchAndSync.scala @@ -2,7 +2,7 @@ package sifive.blocks.util import Chisel._ -import util.AsyncResetRegVec +import freechips.rocketchip.util.AsyncResetRegVec /** Reset: asynchronous assert, * synchronous de-assert diff --git a/src/main/scala/util/Timer.scala b/src/main/scala/util/Timer.scala index e0cba87..52bbab2 100644 --- a/src/main/scala/util/Timer.scala +++ b/src/main/scala/util/Timer.scala @@ -3,8 +3,8 @@ package sifive.blocks.util import Chisel._ import Chisel.ImplicitConversions._ -import regmapper._ -import util.WideCounter +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.util.WideCounter class SlaveRegIF(w: Int) extends Bundle { val write = Valid(UInt(width = w)).flip