From: Megan Wachs <megan@sifive.com>
Date: Wed, 6 Sep 2017 17:59:07 +0000 (-0700)
Subject: shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate
X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=refs%2Fheads%2Fsynchronizers

shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate
---

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index 9bbc576..6bf40ae 100644
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -3,7 +3,7 @@ package sifive.blocks.devices.i2c
 
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
-import freechips.rocketchip.util.SynchronizerShiftRegInit
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 
 class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
@@ -18,12 +18,12 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
       scl.o.oe := i2c.scl.oe
-      i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true),
+      i2c.scl.in := SyncResetSynchronizerShiftReg(scl.i.ival, syncStages, init = Bool(true),
         name = Some("i2c_scl_sync"))
 
       sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
       sda.o.oe := i2c.sda.oe
-      i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true),
+      i2c.sda.in := SyncResetSynchronizerShiftReg(sda.i.ival, syncStages, init = Bool(true),
         name = Some("i2c_sda_sync"))
     }
   }
diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala
index 25ad882..0336aef 100644
--- a/src/main/scala/devices/spi/SPIPhysical.scala
+++ b/src/main/scala/devices/spi/SPIPhysical.scala
@@ -2,7 +2,7 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import freechipchips.rocketchip.util.ShiftRegInit
+import freechips.rocketchip.util.ShiftRegInit
 
 class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
   val fn = Bits(width = 1)
diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 01ae55c..f29716c 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.uart
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.util.SynchronizerShiftRegInit
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import sifive.blocks.devices.pinctrl.{Pin}
@@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       txd.outputPin(uart.txd)
       val rxd_t = rxd.inputPin()
-      uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
+      uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
     }
   }
 }