From aa6d911c265e822bc34f48872838fc3077473f7a Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 25 Jul 2017 08:36:28 -0700 Subject: [PATCH] Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant --- src/main/scala/devices/gpio/GPIOPins.scala | 2 +- src/main/scala/devices/i2c/I2CPins.scala | 2 +- .../devices/{gpio/JTAG.scala => jtag/JTAGPins.scala} | 11 +++++------ src/main/scala/devices/pwm/PWMPeriphery.scala | 2 +- src/main/scala/devices/spi/SPIPins.scala | 2 +- src/main/scala/devices/uart/UARTPeriphery.scala | 2 +- 6 files changed, 10 insertions(+), 11 deletions(-) rename src/main/scala/devices/{gpio/JTAG.scala => jtag/JTAGPins.scala} (78%) diff --git a/src/main/scala/devices/gpio/GPIOPins.scala b/src/main/scala/devices/gpio/GPIOPins.scala index 11723c4..de086bf 100644 --- a/src/main/scala/devices/gpio/GPIOPins.scala +++ b/src/main/scala/devices/gpio/GPIOPins.scala @@ -16,7 +16,7 @@ class GPIOPins[T <: Pin] (pingen: ()=> T, c: GPIOParams) extends Bundle { override def cloneType: this.type = this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] - def fromGPIOPort(port: GPIOPortIO){ + def fromPort(port: GPIOPortIO){ // This will just match up the components of the Bundle that // exist in both. diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala index 8e17765..bae0bc6 100644 --- a/src/main/scala/devices/i2c/I2CPins.scala +++ b/src/main/scala/devices/i2c/I2CPins.scala @@ -15,7 +15,7 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle { override def cloneType: this.type = this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] - def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = { + def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = { withClockAndReset(clock, reset) { scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B) scl.o.oe := i2c.scl.oe diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/jtag/JTAGPins.scala similarity index 78% rename from src/main/scala/devices/gpio/JTAG.scala rename to src/main/scala/devices/jtag/JTAGPins.scala index e10f19b..342f2b9 100644 --- a/src/main/scala/devices/gpio/JTAG.scala +++ b/src/main/scala/devices/jtag/JTAGPins.scala @@ -1,13 +1,12 @@ // See LICENSE for license details. -package sifive.blocks.devices.gpio +package sifive.blocks.devices.jtag import Chisel._ // ------------------------------------------------------------ -// SPI, UART, etc are with their -// respective packages, -// This file is for those that don't seem to have a good place -// to put them otherwise. +// SPI, UART, etc are with their respective packages, +// JTAG doesn't really correspond directly to a device, but it does +// define pins as those devices do. // ------------------------------------------------------------ import freechips.rocketchip.config._ @@ -22,7 +21,7 @@ class JTAGPins[T <: Pin](pingen: () => T, hasTRSTn: Boolean = true) extends Bund val TDO = pingen() val TRSTn = if (hasTRSTn) Option(pingen()) else None - def fromJTAGPort(jtag: JTAGIO): Unit = { + def fromPort(jtag: JTAGIO): Unit = { jtag.TCK := TCK.inputPin (pue = Bool(true)).asClock jtag.TMS := TMS.inputPin (pue = Bool(true)) jtag.TDI := TDI.inputPin(pue = Bool(true)) diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala index ff5b6bb..3754f71 100644 --- a/src/main/scala/devices/pwm/PWMPeriphery.scala +++ b/src/main/scala/devices/pwm/PWMPeriphery.scala @@ -20,7 +20,7 @@ class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle { override def cloneType: this.type = this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] - def fromPWMPort(port: PWMPortIO) { + def fromPort(port: PWMPortIO) { (pwm zip port.port) foreach {case (pin, port) => pin.outputPin(port) } diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala index 4307fad..780e8cc 100644 --- a/src/main/scala/devices/spi/SPIPins.scala +++ b/src/main/scala/devices/spi/SPIPins.scala @@ -14,7 +14,7 @@ class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) override def cloneType: this.type = this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] - def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool, + def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool, syncStages: Int = 0, driveStrength: Bool = Bool(false)) { withClockAndReset(clock, reset) { diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index 5564fef..cb79845 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -47,7 +47,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle { override def cloneType: this.type = this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] - def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) { + def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) { withClockAndReset(clock, reset) { txd.outputPin(uart.txd) val rxd_t = rxd.inputPin() -- 2.30.2