From 015f87ec6b355c0876955b174d5b64300569d68d Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 2 Aug 2017 11:46:27 -0700 Subject: [PATCH] allow bundle content params to be specified via a def (#29) --- src/main/scala/devices/gpio/GPIO.scala | 2 +- src/main/scala/devices/pwm/PWM.scala | 2 +- src/main/scala/devices/uart/UARTPeriphery.scala | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala index e7a4829..2bb04fe 100644 --- a/src/main/scala/devices/gpio/GPIO.scala +++ b/src/main/scala/devices/gpio/GPIO.scala @@ -82,7 +82,7 @@ class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) { // It would be better if the IOF were here and // we could do the pinmux inside. trait HasGPIOBundleContents extends Bundle { - val params: GPIOParams + def params: GPIOParams val port = new GPIOPortIO(params) } diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala index 044d1bd..3d35d81 100644 --- a/src/main/scala/devices/pwm/PWM.scala +++ b/src/main/scala/devices/pwm/PWM.scala @@ -44,7 +44,7 @@ case class PWMParams( cmpWidth: Int = 16) trait HasPWMBundleContents extends Bundle { - val params: PWMParams + def params: PWMParams val gpio = Vec(params.ncmp, Bool()).asOutput } diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index cb79845..00e5fdd 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -12,10 +12,10 @@ import sifive.blocks.util.ShiftRegisterInit case object PeripheryUARTKey extends Field[Seq[UARTParams]] trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus { - val uartParams = p(PeripheryUARTKey) - val divinit = (p(PeripheryBusParams).frequency / 115200).toInt + private val divinit = (p(PeripheryBusParams).frequency / 115200).toInt + val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit)) val uarts = uartParams map { params => - val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit))) + val uart = LazyModule(new TLUART(pbus.beatBytes, params)) uart.node := pbus.toVariableWidthSlaves ibus.fromSync := uart.intnode uart -- 2.30.2