From 1feaefe4c5c8e36682f29508b8e5e2ee9c4d7038 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 5 Sep 2017 18:32:37 -0700 Subject: [PATCH] i2c, uart: Use Synchronizer primitives for the inputs --- src/main/scala/devices/i2c/I2CPins.scala | 6 +++--- src/main/scala/devices/uart/UARTPeriphery.scala | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala index 1a02a59..2e29423 100644 --- a/src/main/scala/devices/i2c/I2CPins.scala +++ b/src/main/scala/devices/i2c/I2CPins.scala @@ -3,7 +3,7 @@ package sifive.blocks.devices.i2c import Chisel._ import chisel3.experimental.{withClockAndReset} -import freechips.rocketchip.util.ShiftRegInit +import freechips.rocketchip.util.SynchronizerShiftRegInit import sifive.blocks.devices.pinctrl.{Pin, PinCtrl} class I2CPins[T <: Pin](pingen: () => T) extends Bundle { @@ -18,11 +18,11 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle { withClockAndReset(clock, reset) { scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B) scl.o.oe := i2c.scl.oe - i2c.scl.in := ShiftRegInit(scl.i.ival, syncStages, init = Bool(true)) + i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true)) sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B) sda.o.oe := i2c.sda.oe - i2c.sda.in := ShiftRegInit(sda.i.ival, syncStages, init = Bool(true)) + i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true)) } } } diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index 4a517cb..f24cbad 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -4,7 +4,7 @@ package sifive.blocks.devices.uart import Chisel._ import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.config.Field -import freechips.rocketchip.util.ShiftRegInit +import freechips.rocketchip.util.SynchronizerShiftRegInit import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import sifive.blocks.devices.pinctrl.{Pin} @@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle { withClockAndReset(clock, reset) { txd.outputPin(uart.txd) val rxd_t = rxd.inputPin() - uart.rxd := ShiftRegInit(rxd_t, n = syncStages, init = Bool(true)) + uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true)) } } } -- 2.30.2