From 39287b92159e7f7a25635dfe7cc5cb7dc01488bc Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Sun, 4 Mar 2018 10:29:51 -0800 Subject: [PATCH] Remove cloneTypes in favor of autoclonetype (#51) * Remove cloneTypes in favor of autoclonetype * Consistently use private val for autoclonetype --- src/main/scala/devices/gpio/GPIO.scala | 4 ++-- src/main/scala/devices/gpio/GPIOPins.scala | 10 ++-------- src/main/scala/devices/i2c/I2CPins.scala | 6 +----- src/main/scala/devices/pwm/PWMPeriphery.scala | 1 - src/main/scala/devices/pwm/PWMPins.scala | 8 ++------ src/main/scala/devices/spi/SPIBundle.scala | 6 +----- src/main/scala/devices/spi/SPIPins.scala | 6 +----- src/main/scala/devices/uart/UARTPins.scala | 7 ++----- src/main/scala/util/Timer.scala | 4 +--- 9 files changed, 12 insertions(+), 40 deletions(-) diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala index f5098cf..a1b166f 100644 --- a/src/main/scala/devices/gpio/GPIO.scala +++ b/src/main/scala/devices/gpio/GPIO.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.util.SynchronizerShiftReg import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ -import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle} +import freechips.rocketchip.util.AsyncResetRegVec case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false) @@ -75,7 +75,7 @@ object BasePinToIOF { // level, and we have to do the pinmux // outside of RocketChipTop. -class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) { +class GPIOPortIO(private val c: GPIOParams) extends Bundle { val pins = Vec(c.width, new EnhancedPin()) val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None diff --git a/src/main/scala/devices/gpio/GPIOPins.scala b/src/main/scala/devices/gpio/GPIOPins.scala index 8572923..da6ade3 100644 --- a/src/main/scala/devices/gpio/GPIOPins.scala +++ b/src/main/scala/devices/gpio/GPIOPins.scala @@ -9,17 +9,11 @@ import sifive.blocks.devices.pinctrl.{Pin} // even though it looks like something that more directly talks to // a pin. It also makes it possible to change the exact // type of pad this connects to. -class GPIOSignals[T <: Data] (pingen: ()=> T, c: GPIOParams) extends Bundle { +class GPIOSignals[T <: Data](private val pingen: () => T, private val c: GPIOParams) extends Bundle { val pins = Vec(c.width, pingen()) - - override def cloneType: this.type = - this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] } -class GPIOPins[T <: Pin] (pingen: ()=> T, c: GPIOParams) extends GPIOSignals[T](pingen, c) { - override def cloneType: this.type = - this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] -} +class GPIOPins[T <: Pin](pingen: () => T, c: GPIOParams) extends GPIOSignals[T](pingen, c) object GPIOPinsFromPort { diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala index a4016f3..32cf50d 100644 --- a/src/main/scala/devices/i2c/I2CPins.scala +++ b/src/main/scala/devices/i2c/I2CPins.scala @@ -6,13 +6,9 @@ import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.util.SyncResetSynchronizerShiftReg import sifive.blocks.devices.pinctrl.{Pin, PinCtrl} -class I2CSignals[T <: Data](pingen: () => T) extends Bundle { - +class I2CSignals[T <: Data](private val pingen: () => T) extends Bundle { val scl: T = pingen() val sda: T = pingen() - - override def cloneType: this.type = - this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] } class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen) diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala index e098258..cc2c6ed 100644 --- a/src/main/scala/devices/pwm/PWMPeriphery.scala +++ b/src/main/scala/devices/pwm/PWMPeriphery.scala @@ -10,7 +10,6 @@ import sifive.blocks.devices.pinctrl.{Pin} class PWMPortIO(val c: PWMParams) extends Bundle { val port = Vec(c.ncmp, Bool()).asOutput - override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type] } diff --git a/src/main/scala/devices/pwm/PWMPins.scala b/src/main/scala/devices/pwm/PWMPins.scala index aa7e032..2a9716b 100644 --- a/src/main/scala/devices/pwm/PWMPins.scala +++ b/src/main/scala/devices/pwm/PWMPins.scala @@ -4,15 +4,11 @@ package sifive.blocks.devices.pwm import Chisel._ import sifive.blocks.devices.pinctrl.{Pin} -class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle { - +class PWMSignals[T <: Data](private val pingen: () => T, val c: PWMParams) extends Bundle { val pwm: Vec[T] = Vec(c.ncmp, pingen()) - - override def cloneType: this.type = - this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] } -class PWMPins[T <: Pin] (pingen: ()=> T, c: PWMParams) extends PWMSignals[T](pingen, c) +class PWMPins[T <: Pin](pingen: () => T, c: PWMParams) extends PWMSignals[T](pingen, c) object PWMPinsFromPort { def apply[T <: Pin] (pins: PWMSignals[T], port: PWMPortIO): Unit = { diff --git a/src/main/scala/devices/spi/SPIBundle.scala b/src/main/scala/devices/spi/SPIBundle.scala index 332edff..e7abde6 100644 --- a/src/main/scala/devices/spi/SPIBundle.scala +++ b/src/main/scala/devices/spi/SPIBundle.scala @@ -2,12 +2,8 @@ package sifive.blocks.devices.spi import Chisel._ -import freechips.rocketchip.util.GenericParameterizedBundle -abstract class SPIBundle(val c: SPIParamsBase) extends GenericParameterizedBundle(c) { - override def cloneType: SPIBundle.this.type = - this.getClass.getConstructors.head.newInstance(c).asInstanceOf[this.type] -} +abstract class SPIBundle(private val c: SPIParamsBase) extends Bundle class SPIDataIO extends Bundle { val i = Bool(INPUT) diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala index e380bf9..f8ce8e1 100644 --- a/src/main/scala/devices/spi/SPIPins.scala +++ b/src/main/scala/devices/spi/SPIPins.scala @@ -5,15 +5,11 @@ import Chisel._ import chisel3.experimental.{withClockAndReset} import sifive.blocks.devices.pinctrl.{PinCtrl, Pin} -class SPISignals[T <: Data] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) { +class SPISignals[T <: Data](private val pingen: () => T, c: SPIParamsBase) extends SPIBundle(c) { val sck = pingen() val dq = Vec(4, pingen()) val cs = Vec(c.csWidth, pingen()) - - override def cloneType: this.type = - this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] - } class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c) diff --git a/src/main/scala/devices/uart/UARTPins.scala b/src/main/scala/devices/uart/UARTPins.scala index aeb3632..88fa34c 100644 --- a/src/main/scala/devices/uart/UARTPins.scala +++ b/src/main/scala/devices/uart/UARTPins.scala @@ -6,15 +6,12 @@ import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.util.SyncResetSynchronizerShiftReg import sifive.blocks.devices.pinctrl.{Pin} -class UARTSignals[T <: Data] (pingen: () => T) extends Bundle { +class UARTSignals[T <: Data](private val pingen: () => T) extends Bundle { val rxd = pingen() val txd = pingen() - - override def cloneType: this.type = - this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] } -class UARTPins[T <: Pin] (pingen: () => T) extends UARTSignals[T](pingen) +class UARTPins[T <: Pin](pingen: () => T) extends UARTSignals[T](pingen) object UARTPinsFromPort { def apply[T <: Pin](pins: UARTSignals[T], uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) { diff --git a/src/main/scala/util/Timer.scala b/src/main/scala/util/Timer.scala index c46d2be..35e4a83 100644 --- a/src/main/scala/util/Timer.scala +++ b/src/main/scala/util/Timer.scala @@ -6,12 +6,10 @@ import Chisel.ImplicitConversions._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.util.WideCounter -class SlaveRegIF(w: Int) extends Bundle { +class SlaveRegIF(private val w: Int) extends Bundle { val write = Valid(UInt(width = w)).flip val read = UInt(OUTPUT, w) - override def cloneType: this.type = new SlaveRegIF(w).asInstanceOf[this.type] - def toRegField(dummy: Int = 0): RegField = { def writeFn(valid: Bool, data: UInt): Bool = { write.valid := valid -- 2.30.2