From 48222bcd2d8f5e3afeabf05719225b11737c6baa Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 5 Sep 2017 18:35:09 -0700 Subject: [PATCH] gpio: Use Synchronizer for the inputs --- src/main/scala/devices/gpio/GPIO.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala index 2bb04fe..d4cd24e 100644 --- a/src/main/scala/devices/gpio/GPIO.scala +++ b/src/main/scala/devices/gpio/GPIO.scala @@ -4,6 +4,7 @@ package sifive.blocks.devices.gpio import Chisel._ import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl} import freechips.rocketchip.config.Parameters +import freechips.rocketchip.util.SynchronizerShiftReg import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle} @@ -106,7 +107,7 @@ trait HasGPIOModuleContents extends Module with HasRegMap { // Synchronize Input to get valueReg val inVal = Wire(UInt(0, width=c.width)) inVal := Vec(io.port.pins.map(_.i.ival)).asUInt - val inSyncReg = ShiftRegister(inVal, 3) + val inSyncReg = SynchronizerShiftReg(inVal, 3, Some("inSyncReg")) val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg) // Interrupt Configuration -- 2.30.2