From b1dfcfc0b0c303ac40c55be208e01e9dca16665e Mon Sep 17 00:00:00 2001 From: solomatnikov Date: Tue, 25 Apr 2017 09:14:00 -0700 Subject: [PATCH] Added stall for read after write (#8) --- src/main/scala/devices/i2c/I2C.scala | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala index 7b9fad8..f0df22a 100644 --- a/src/main/scala/devices/i2c/I2C.scala +++ b/src/main/scala/devices/i2c/I2C.scala @@ -517,12 +517,28 @@ trait HasI2CModuleContents extends Module with HasRegMap { status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck + val statusReadReady = Reg(init = true.B) + when (!statusReadReady) { + statusReadReady := true.B + } + + // statusReadReady, regmap( I2CCtrlRegs.prescaler_lo -> Seq(RegField(8, prescaler.lo)), I2CCtrlRegs.prescaler_hi -> Seq(RegField(8, prescaler.hi)), I2CCtrlRegs.control -> control.elements.map{ case(name, e) => RegField(e.getWidth, e.asInstanceOf[UInt]) }.toSeq, I2CCtrlRegs.data -> Seq(RegField(8, r = RegReadFn(receivedData), w = RegWriteFn(transmitData))), - I2CCtrlRegs.cmd_status -> Seq(RegField(8, r = RegReadFn(status.asUInt), w = RegWriteFn(nextCmd))) + I2CCtrlRegs.cmd_status -> Seq(RegField(8, r = RegReadFn{ ready => + (statusReadReady, status.asUInt) + }, + w = RegWriteFn((valid, data) => { + when (valid) { + statusReadReady := false.B + nextCmd := data + } + true.B + } + ))) ) // tie off unused bits -- 2.30.2