From 249c23e617496b2ecd5baea3b0df672db2d62d61 Mon Sep 17 00:00:00 2001
From: Shreesha Srinath <shreesha@sifive.com>
Date: Thu, 17 Aug 2017 18:22:51 -0700
Subject: [PATCH] Renamed ShiftReg to ShiftRegister

---
 src/main/scala/util/{ShiftReg.scala => ShiftRegister.scala} | 3 +++
 1 file changed, 3 insertions(+)
 rename src/main/scala/util/{ShiftReg.scala => ShiftRegister.scala} (92%)

diff --git a/src/main/scala/util/ShiftReg.scala b/src/main/scala/util/ShiftRegister.scala
similarity index 92%
rename from src/main/scala/util/ShiftReg.scala
rename to src/main/scala/util/ShiftRegister.scala
index 37719a7..574c4b7 100644
--- a/src/main/scala/util/ShiftReg.scala
+++ b/src/main/scala/util/ShiftRegister.scala
@@ -10,6 +10,9 @@ object ShiftRegisterInit {
     }
 }
 
+
+// Similar to the Chisel ShiftRegister but allows the user to suggest a
+// name to the registers within the module that get instantiated
 object ShiftRegister
 {
   /** Returns the n-cycle delayed version of the input signal.
-- 
2.30.2