From 3d8c502fce3f4920b226026c07fd47325af5fba1 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Jun 2017 17:45:18 -0700 Subject: [PATCH] diplomacy: add reg-names to devices (#22) --- src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala | 2 +- .../ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala index f6ae153..931e9be 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala @@ -24,7 +24,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)), - resources = device.reg, + resources = device.reg("mem"), regionType = RegionType.UNCACHED, executable = true, supportsWrite = TransferSizes(1, 256*8), diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala index ac9745f..c7206e4 100644 --- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala @@ -181,8 +181,8 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule "device_type" -> Seq(ResourceString("pci")), "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), - "ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _, _)) => - ResourceMapping(address, BigInt(0x02000000) << 64) }, + "ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, perms)) => + ResourceMapping(address, BigInt(0x02000000) << 64, perms) }, "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( "interrupt-controller" -> Nil, "#address-cells" -> ofInt(0), @@ -203,7 +203,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( address = List(AddressSet(0x50000000L, 0x03ffffffL)), - resources = device.reg, + resources = device.reg("control"), supportsWrite = TransferSizes(1, 4), supportsRead = TransferSizes(1, 4), interleavedId = Some(0))), // AXI4-Lite never interleaves responses -- 2.30.2