From 5d1e9b793a0fd910abe4dbbf79c63cb51b0bc8df Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 22 Sep 2017 13:55:55 -0700 Subject: [PATCH] signal_bundles: add missing file --- src/main/scala/devices/pwm/PWMPins.scala | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 src/main/scala/devices/pwm/PWMPins.scala diff --git a/src/main/scala/devices/pwm/PWMPins.scala b/src/main/scala/devices/pwm/PWMPins.scala new file mode 100644 index 0000000..7ab76f0 --- /dev/null +++ b/src/main/scala/devices/pwm/PWMPins.scala @@ -0,0 +1,27 @@ +// See LICENSE for license details. +package sifive.blocks.devices.pwm + +import Chisel._ +import freechips.rocketchip.config.Field +import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} +import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.util.HeterogeneousBag +import sifive.blocks.devices.pinctrl.{Pin} + +class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle { + + val pwm: Vec[T] = Vec(c.ncmp, pingen()) + + override def cloneType: this.type = + this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] +} + +class PWMPins[T <: Pin] (pingen: ()=> T, c: PWMParams) extends PWMSignals[T](pingen, c) + +object PWMPinsFromPort { + def apply[T <: Pin] (pins: PWMSignals[T], port: PWMPortIO): Unit = { + (pins.pwm zip port.port) foreach {case (pin, port) => + pin.outputPin(port) + } + } +} -- 2.30.2