From 90d3931f5aa22f00c3f6472e0b48c3a9b150db08 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 14 Jun 2017 17:06:55 -0700 Subject: [PATCH] spi: add dts ranges field for memory mapped spi (#19) --- src/main/scala/devices/spi/TLSPI.scala | 10 +++++++++- src/main/scala/devices/spi/TLSPIFlash.scala | 1 + 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala index 5c5b9bf..5833fad 100644 --- a/src/main/scala/devices/spi/TLSPI.scala +++ b/src/main/scala/devices/spi/TLSPI.scala @@ -109,7 +109,15 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule { require(isPow2(c.rSize)) - val device = new SimpleDevice("spi", Seq("sifive,spi0")) + val device = new SimpleDevice("spi", Seq("sifive,spi0")) { + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + val rangesSeq = resources("ranges").map(_.value) + val ranges = if (rangesSeq.isEmpty) Map() else Map("ranges" -> rangesSeq) + Description(name, mapping ++ ranges) + } + } + val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w) val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int)) } diff --git a/src/main/scala/devices/spi/TLSPIFlash.scala b/src/main/scala/devices/spi/TLSPIFlash.scala index 752aa5f..fc786f5 100644 --- a/src/main/scala/devices/spi/TLSPIFlash.scala +++ b/src/main/scala/devices/spi/TLSPIFlash.scala @@ -95,6 +95,7 @@ abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Paramet require(isPow2(c.fSize)) val fnode = TLManagerNode(1, TLManagerParameters( address = Seq(AddressSet(c.fAddress, c.fSize-1)), + resources = Seq(Resource(device, "ranges")), regionType = RegionType.UNCACHED, executable = true, supportsGet = TransferSizes(1, 1), -- 2.30.2