1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Mux
, Elaboratable
5 from nmutil
.latch
import SRLatch
, latchregister
7 """ Computation Unit (aka "ALU Manager").
9 This module runs a "revolving door" set of three latches, based on
13 where one of them cannot be set on any given cycle.
14 (Note however that opc_l has been inverted (and qn used), due to SRLatch
15 default reset state being "0" rather than "1")
17 * When issue is first raised, a busy signal is sent out.
18 The src1 and src2 registers and the operand can be latched in
21 * Read request is set, which is acknowledged through the Scoreboard
22 to the priority picker, which generates (one and only one) Go_Read
23 at a time. One of those will (eventually) be this Computation Unit.
25 * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
26 src1/src2/operand in place), and the ALU is told to proceed.
28 * As this is currently a "demo" unit, a countdown timer is activated
29 to simulate an ALU "pipeline", which activates "write request release",
30 and the ALU's output is captured into a temporary register.
32 * Write request release will go through a similar process as Read request,
33 resulting (eventually) in Go_Write being asserted.
35 * When Go_Write is asserted, two things happen: (1) the data in the temp
36 register is placed combinatorially onto the output, and (2) the
37 req_l latch is cleared, busy is dropped, and the Comp Unit is back
38 through its revolving door to do another task.
42 * bits[0:2] are for the ALU, add=0, sub=1, shift=2, mul=3
43 * bit[2] are the immediate (bit[2]=1 == immediate mode)
46 class ComputationUnitNoDelay(Elaboratable
):
47 def __init__(self
, rwid
, opwid
, alu
):
52 self
.counter
= Signal(4)
53 self
.go_rd_i
= Signal(reset_less
=True) # go read in
54 self
.go_wr_i
= Signal(reset_less
=True) # go write in
55 self
.issue_i
= Signal(reset_less
=True) # fn issue in
56 self
.shadown_i
= Signal(reset
=1) # shadow function, defaults to ON
57 self
.go_die_i
= Signal() # go die (reset)
59 self
.oper_i
= Signal(opwid
, reset_less
=True) # opcode in
60 self
.imm_i
= Signal(rwid
, reset_less
=True) # immediate in
61 self
.src1_i
= Signal(rwid
, reset_less
=True) # oper1 in
62 self
.src2_i
= Signal(rwid
, reset_less
=True) # oper2 in
64 self
.busy_o
= Signal(reset_less
=True) # fn busy out
65 self
.data_o
= Signal(rwid
, reset_less
=True) # Dest out
66 self
.rd_rel_o
= Signal(reset_less
=True) # release src1/src2 request
67 self
.req_rel_o
= Signal(reset_less
=True) # release request out (valid_o)
68 self
.done_o
= self
.req_rel_o
# 'normalise' API
70 def elaborate(self
, platform
):
72 m
.submodules
.alu
= self
.alu
73 m
.submodules
.src_l
= src_l
= SRLatch(sync
=False)
74 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False)
75 m
.submodules
.req_l
= req_l
= SRLatch(sync
=False)
78 reset_w
= Signal(reset_less
=True)
79 reset_r
= Signal(reset_less
=True)
80 m
.d
.comb
+= reset_w
.eq(self
.go_wr_i | self
.go_die_i
)
81 m
.d
.comb
+= reset_r
.eq(self
.go_rd_i | self
.go_die_i
)
83 # This is fascinating and very important to observe that this
84 # is in effect a "3-way revolving door". At no time may all 3
85 # latches be set at the same time.
87 # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
88 m
.d
.sync
+= opc_l
.s
.eq(self
.issue_i
) # XXX NOTE: INVERTED FROM book!
89 m
.d
.sync
+= opc_l
.r
.eq(reset_w
) # XXX NOTE: INVERTED FROM book!
91 # src operand latch (not using go_wr_i)
92 m
.d
.sync
+= src_l
.s
.eq(self
.issue_i
)
93 m
.d
.sync
+= src_l
.r
.eq(reset_r
)
95 # dest operand latch (not using issue_i)
96 m
.d
.sync
+= req_l
.s
.eq(self
.go_rd_i
)
97 m
.d
.sync
+= req_l
.r
.eq(reset_w
)
100 # create a latch/register for the operand
101 oper_r
= Signal(self
.opwid
+1, reset_less
=True) # opcode reg
102 latchregister(m
, self
.oper_i
, oper_r
, self
.issue_i
)
104 # and one for the output from the ALU
105 data_r
= Signal(self
.rwid
, reset_less
=True) # Dest register
106 latchregister(m
, self
.alu
.o
, data_r
, req_l
.q
)
108 # get the top 2 bits for the ALU
109 m
.d
.comb
+= self
.alu
.op
.eq(oper_r
[0:2])
111 # 3rd bit is whether this is an immediate or not
112 op_is_imm
= Signal(reset_less
=True)
113 m
.d
.comb
+= op_is_imm
.eq(oper_r
[2])
115 # select immediate if opcode says so. however also change the latch
116 # to trigger *from* the opcode latch instead.
117 src2_or_imm
= Signal(self
.rwid
, reset_less
=True)
118 src_sel
= Signal(reset_less
=True)
119 m
.d
.comb
+= src_sel
.eq(Mux(op_is_imm
, opc_l
.qn
, src_l
.q
))
120 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, self
.imm_i
, self
.src2_i
))
122 # create a latch/register for src1/src2
123 latchregister(m
, self
.src1_i
, self
.alu
.a
, src_l
.q
)
124 latchregister(m
, src2_or_imm
, self
.alu
.b
, src_sel
)
130 # all request signals gated by busy_o. prevents picker problems
132 m
.d
.comb
+= busy_o
.eq(opc_l
.q
) # busy out
133 m
.d
.comb
+= self
.rd_rel_o
.eq(src_l
.q
& busy_o
) # src1/src2 req rel
135 # on a go_read, tell the ALU we're accepting data.
136 # NOTE: this spells TROUBLE if the ALU isn't ready!
137 # go_read is only valid for one clock!
138 with m
.If(self
.go_rd_i
): # src operands ready, GO!
139 with m
.If(~self
.alu
.p_ready_o
): # no ACK yet
140 m
.d
.comb
+= self
.alu
.p_valid_i
.eq(1) # so indicate valid
142 # only proceed if ALU says its output is valid
143 with m
.If(self
.alu
.n_valid_o
):
144 # when ALU ready, write req release out. waits for shadow
145 m
.d
.comb
+= self
.req_rel_o
.eq(req_l
.q
& busy_o
& self
.shadown_i
)
146 # when output latch is ready, and ALU says ready, accept ALU output
147 with m
.If(self
.req_rel_o
):
148 m
.d
.comb
+= self
.alu
.n_ready_i
.eq(1) # tells ALU "thanks got it"
150 # output the data from the latch on go_write
151 with m
.If(self
.go_wr_i
):
152 m
.d
.comb
+= self
.data_o
.eq(data_r
)
175 def scoreboard_sim(dut
):
176 yield dut
.dest_i
.eq(1)
177 yield dut
.issue_i
.eq(1)
179 yield dut
.issue_i
.eq(0)
181 yield dut
.src1_i
.eq(1)
182 yield dut
.issue_i
.eq(1)
186 yield dut
.issue_i
.eq(0)
188 yield dut
.go_read_i
.eq(1)
190 yield dut
.go_read_i
.eq(0)
192 yield dut
.go_write_i
.eq(1)
194 yield dut
.go_write_i
.eq(0)
197 def test_scoreboard():
198 from alu_hier
import ALU
200 dut
= ComputationUnitNoDelay(16, 8, alu
)
201 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
202 with
open("test_compalu.il", "w") as f
:
205 run_simulation(dut
, scoreboard_sim(dut
), vcd_name
='test_compalu.vcd')
207 if __name__
== '__main__':