X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=Makefile;h=185a0d223124d60253041a59d1f53835adc84df3;hp=736cd7b1ac2ace8e379e6a941d3e1f0adaf4c0de;hb=HEAD;hpb=b263f3f6f134c2f1d9be78d69b1799b3fbd90b4d

diff --git a/Makefile b/Makefile
index 736cd7b1..15670cf8 100644
--- a/Makefile
+++ b/Makefile
@@ -63,16 +63,34 @@ microwatt_external_core:
 	python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
             external_core_top.v
 
+# build microwatt "external core" with fixed 64-bit width SVP64
+# note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
+microwatt_external_core_svp64:
+	python3 src/soc/simple/issuer_verilog.py --microwatt-compat-svp64 --enable-mmu \
+            external_core_top.v
+
 microwatt_external_core_spi:
 	python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --small-cache \
             --enable-mmu \
             --pc-reset 0x10000000 \
             external_core_top.v
 
+# microwatt-compatible core with smaller cache size (quick. VERSA_ECP5. just)
 microwatt_external_core_bram:
+	python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --small-cache \
+            --enable-mmu \
+            --pc-reset 0xFF000000 \
+            external_core_top.v
+
+# microwatt-compatible core with larger cache size (experiment on arty)
+microwatt_external_core_bram_arty:
 	python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
             --enable-mmu \
-            --pc-reset 0xFFF00000 \
+            --pc-reset 0xFF000000 \
             external_core_top.v
 
 # build the litex libresoc SoC without 4k SRAMs