X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=blobdiff_plain;f=src%2FTLB%2FTLB.py;h=2feaf4b70e0a6f4f044b28ab263cb64712da7186;hp=f2b7a9250e1dd9d2daa37a9bd672f82a685c05be;hb=8db2c7353efa0885d95a00a55435959390bbc947;hpb=b7aad51f4f5a13a86f347d33abdac841d74a70bd

diff --git a/src/TLB/TLB.py b/src/TLB/TLB.py
index f2b7a925..2feaf4b7 100644
--- a/src/TLB/TLB.py
+++ b/src/TLB/TLB.py
@@ -27,7 +27,7 @@ class TLB(Elaboratable):
         # Internal
         self.state = 0
         # L1 Cache Modules
-        L1_size = 8 # XXX overridden incoming argument?
+        ### L1_size = 8 # XXX overridden incoming argument?
         self.cam_L1 = Cam(vma_size, L1_size)
         self.mem_L1 = Memory(asid_size + pte_size, L1_size)
 
@@ -124,11 +124,12 @@ class TLB(Elaboratable):
         m = Module()
         # Add submodules
         # Submodules for L1 Cache
-        m.d.submodules.cam_L1 = self.cam_L1
-        m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port()
-        m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.write_port()
+        m.submodules.cam_L1 = self.cam_L1
+        m.submodules.read_L1 = read_L1 = self.mem_L1.read_port()
+        m.submodules.write_L1 = write_L1 = self.mem_L1.write_port()
+        
         # Permission Validator Submodule
-        m.d.submodules.perm_valididator = self.perm_validator
+        m.submodules.perm_valididator = self.perm_validator
 
         # When MODE specifies translation
         # TODO add in different bit length handling ie prefix 0s