add radix MMU "miss" test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 14 May 2021 19:47:38 +0000 (20:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 14 May 2021 19:47:38 +0000 (20:47 +0100)
commit0b3c49922c2855c6c1a3fa2e30fa31a4813f895d
tree6d747b13d4844b309026cd3035f9dceff14f73e7
parent81cc035ce036f27e4caa409cb8b799e2e00e0f6a
add radix MMU "miss" test
src/soc/experiment/test/test_ldst_pi.py