add SRR1 setting for LDST memory exception trap
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 6 Oct 2020 15:58:14 +0000 (16:58 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 6 Oct 2020 15:58:14 +0000 (16:58 +0100)
commit20afbd096e75c1fa88f6ba07a5d7804b76b8a971
treec404c0be3e2e9fee7cdaff9e6f8fabff9871491d
parentd1a85475871bb00adb8d5827008cb293e1e8d966
add SRR1 setting for LDST memory exception trap
src/soc/consts.py
src/soc/decoder/power_decoder2.py
src/soc/fu/trap/main_stage.py