add detection of whether *full* 7-bit of RA is zero/non-zero
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 11 Mar 2021 19:50:19 +0000 (19:50 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 11 Mar 2021 19:50:19 +0000 (19:50 +0000)
commit4b96305143765fa4a44627d0dce7fca870a4552a
tree69f71254b87cb5471fe3b091ade65cfbeb1f3a25
parent30bb35201ebf726934ad619a38f1b9f5df5d4bde
add detection of whether *full* 7-bit of RA is zero/non-zero
this because RA_OR_ZERO in PowerDecoder2 needs to test if the full
SVP64-extended register is zero
src/soc/decoder/isa/test_caller_svp64.py
src/soc/decoder/power_decoder2.py