projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 4fb3d7f) | patch
Implement transparent read ports on the phased write SRAM
authorCesar Strauss <cestrauss@gmail.com>
Sat, 2 Apr 2022 20:46:29 +0000 (17:46 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sat, 2 Apr 2022 20:46:29 +0000 (17:46 -0300)
commit4e640592205086f2dfce158ec19296e4d6817513
tree2d1ccb0f70f8b8e369e8bc8e14b72918cf4874d8tree
parent4fb3d7fb6c492cfbc0dfb9039c8bd126df753e96commit | diff
Implement transparent read ports on the phased write SRAM

Add a multiplexer to select the write memory instead of the read
memory, in case both port addresses coincide.
src/soc/regfile/sram_wrapper.py diff | blob | history