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(parent: 9885585) | patch
yet more debug log stuff for DCache, this time on CacheRam, to discern
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 13 May 2021 19:02:00 +0000 (20:02 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 13 May 2021 19:02:00 +0000 (20:02 +0100)
commit7dad1f35c256d6518a7e83dfe7330700586ce240
tree05070c347402f849f40a911c6892153883b52727tree
parent9885585d097ca1f26283fa9dc0f22a4fa7bc026ccommit | diff
yet more debug log stuff for DCache, this time on CacheRam, to discern
which SRAM the read/write request went to
src/soc/experiment/cache_ram.py diff | blob | history
src/soc/experiment/dcache.py diff | blob | history