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(parent: c2f68b7) | patch
sort out PLL domains but bypass PLL due to lack of time
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Jun 2021 14:41:33 +0000 (15:41 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Jun 2021 14:41:33 +0000 (15:41 +0100)
commit8ff926f489b50da22fcd00c53bbde79f1659c52d
tree8d6dcd3c6332c731fea9dc79216fc0a7e8602ab6tree
parentc2f68b77a6cea017931cbd714a71a5303c10103acommit | diff
sort out PLL domains but bypass PLL due to lack of time
src/soc/debug/jtag.py diff | blob | history
src/soc/simple/issuer.py diff | blob | history