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(parent: 4c91ccb) | patch
hmm there seems to have been an error in DTLB Read,
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 24 Jan 2022 14:11:07 +0000 (14:11 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 24 Jan 2022 14:11:07 +0000 (14:11 +0000)
commit9c10fda22f62420e78048fa3139e3772744b53fe
tree5a446c7ec72d8c2a05a9b2f21cece172229fa9c1tree
parent4c91ccb579fe45712133572a33e2bd57cb184236commit | diff
hmm there seems to have been an error in DTLB Read,
where if a write *and* a read occurred at the same time, the old
DTLB-valid entry was given. add similar "forwarding" that is used in
Memory.  DTLB-valid is actually a register not a Memory, where the
DTLB way/tags are a Memory, hence the bug
src/soc/experiment/dcache.py diff | blob | history