add DEC SPR to CoreState and PowerDecoder, activate 0x900 interrupt
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 6 Sep 2020 11:13:16 +0000 (12:13 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 6 Sep 2020 11:13:16 +0000 (12:13 +0100)
commita645950fa2d3c64b63b187485034dbafd115a16d
tree61de887b5d0073beb62897cb7c3dfd5cfd3803e1
parent16bb624e1c24519914e30e767139fe8c64d46da6
add DEC SPR to CoreState and PowerDecoder, activate 0x900 interrupt
src/soc/config/state.py
src/soc/consts.py
src/soc/decoder/power_decoder2.py