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(parent: a9e40b6) | patch
ISI (0x400) trap is the only one that puts memory-based exception
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 19 Jan 2022 17:18:35 +0000 (17:18 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 19 Jan 2022 17:18:35 +0000 (17:18 +0000)
commitaa6f072ab1d32e5439c98f012671aab577e7e5eb
tree8a87d1a239f81dc9d950e89256c4f816a5636060tree
parenta9e40b696f5d4f243efecffd758090439b89f005commit | diff
ISI (0x400) trap is the only one that puts memory-based exception
info into SRR1, not *all* memory-based exceptions
src/soc/debug/dmi.py diff | blob | history
src/soc/fu/spr/main_stage.py diff | blob | history
src/soc/fu/trap/main_stage.py diff | blob | history