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(parent: 7e720f6) | patch
add auto-generation of out2 column in SVP64RM
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 18 Mar 2021 12:13:20 +0000 (12:13 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 18 Mar 2021 12:13:20 +0000 (12:13 +0000)
commitb6fdac253479a66f25fbb33f34f07c18ce7d222b
tree46f1c81f17649daf7398ba43fc1ee3c62b522dfatree
parent7e720f6e48cbd1985904a4917c60c6ea148d4e55commit | diff
add auto-generation of out2 column in SVP64RM
needed for PowerDecoder2 as well as microwatt svp64 vhdl generation
Makefile diff | blob | history
libreriscv diff | blob | history
src/soc/decoder/power_svp64.py diff | blob | history