rename PLL signals
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 25 May 2021 11:31:31 +0000 (12:31 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 26 May 2021 13:22:49 +0000 (14:22 +0100)
commitc6ad07b572b06e2606e404738284e01c3c791dd5
treeeccdb2d12625849e15aa4a8bfc6890499f6492b9
parent32b0d64c91ac2830e6526f1a020c9402fb208ad0
rename PLL signals
src/soc/clock/dummypll.py
src/soc/simple/issuer.py