projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: e19f8c2) | patch
strip first 3 bits of WB address from microwatt d/i-bus, bug in microwatt
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Feb 2022 14:22:48 +0000 (14:22 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Feb 2022 14:22:48 +0000 (14:22 +0000)
commitcf9b19e144fc1d035b719be445b7b10373674389
tree205329f4d8e0f34f0570f4f2ff96f77d8cdaa3b8tree
parente19f8c221914c76270d0059455279c63a65e69e9commit | diff
strip first 3 bits of WB address from microwatt d/i-bus, bug in microwatt
src/soc/bus/external_core.py diff | blob | history