rename and add pll lock signal to ls180
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 13 Nov 2020 16:10:42 +0000 (16:10 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 13 Nov 2020 16:10:42 +0000 (16:10 +0000)
commite8a73e28939598ec2b7d1b4c6c73cef4afb93e07
tree9601e5e7118039d13c1ca78be8a3daa481eee0aa
parent6ec3d32ed28acca2d301512876d3ae6f7b45ad78
rename and add pll lock signal to ls180
src/soc/clock/dummypll.py
src/soc/litex/florent/libresoc/core.py
src/soc/litex/florent/libresoc/ls180.py
src/soc/litex/florent/ls180soc.py
src/soc/simple/issuer.py