forgot to pass cix (cache-inhibited) through to LD/ST which was

forgot to pass cix (cache-inhibited) through to LD/ST which was
causing D-Cache to make too many read/writes and overrun wishbone
bus addressing on peripherals.
D-Cache always (for non-cache-inhibited) makes 8 64-bit requests:
if a memory-mapped peripheral has only say 3 32-bit CSRs then the
additional requests beyond the range of the peripheral will cause
a permanent lock-up