move priority picker to nmutil

diff --git a/src/scoreboard/group_picker.py b/src/scoreboard/group_picker.py
index 133b37203a473bfe3cfea73559c589987ccfedf3..a59fdd28eeb4da7347cf1e7a6661b53e8bbb8987 100644 (file)
--- a/src/scoreboard/group_picker.py
+++ b/src/scoreboard/group_picker.py
@@ -1,7 +1,3 @@
-from nmigen.compat.sim import run_simulation
-from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Cat, Elaboratable
-
 """ Group Picker: to select an instruction that is permitted to read (or write)
     based on the Function Unit expressing a *desire* to read (or write).
 
@@ -46,40 +42,11 @@ from nmigen import Module, Signal, Cat, Elaboratable
 
 """
 
-class PriorityPicker(Elaboratable):
-    """ implements a priority-picker.  input: N bits, output: N bits
-    """
-    def __init__(self, wid):
-        self.wid = wid
-        # inputs
-        self.i = Signal(wid, reset_less=True)
-        self.o = Signal(wid, reset_less=True)
-
-    def elaborate(self, platform):
-        m = Module()
-
-        res = []
-        ni = Signal(self.wid, reset_less = True)
-        m.d.comb += ni.eq(~self.i)
-        for i in range(0, self.wid):
-            t = Signal(reset_less = True)
-            res.append(t)
-            if i == 0:
-                m.d.comb += t.eq(self.i[i])
-            else:
-                m.d.comb += t.eq(~Cat(ni[i], *self.i[:i]).bool())
-
-        # we like Cat(*xxx).  turn lists into concatenated bits
-        m.d.comb += self.o.eq(Cat(*res))
-
-        return m
-
-    def __iter__(self):
-        yield self.i
-        yield self.o
+from nmigen.compat.sim import run_simulation
+from nmigen.cli import verilog, rtlil
+from nmigen import Module, Signal, Elaboratable
 
-    def ports(self):
-        return list(self)
+from nmutil.picker import PriorityPicker
 
 
 class GroupPicker(Elaboratable):