From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Feb 2021 15:22:18 +0000 (+0000)
Subject: add litex wishbone interconnect to 4x 4k SRAMs
X-Git-Tag: convert-csv-opcode-to-binary~200
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=0cd474099a8106c81178c6ac1cd507737068d24d

add litex wishbone interconnect to 4x 4k SRAMs
also had to add one more of the massive DFF 512 byte SRAMs in order to cover
all the exception areas (0x900) without going into 4k SRAM area,
which litex demands to be on an aligned boundary
---

diff --git a/Makefile b/Makefile
index cd8c001d..453d0a47 100644
--- a/Makefile
+++ b/Makefile
@@ -29,6 +29,12 @@ testgpio_run_sim:
 	python3 src/soc/litex/florent/sim.py --cpu=libresoc \
 			--variant=standardjtagtestgpio
 
+ls180_verilog:
+	python3 src/soc/simple/issuer_verilog.py \
+	        --debug=jtag --enable-core --enable-pll \
+	        --enable-xics --enable-sram4x4kblock
+			src/soc/litex/florent/libresoc/libresoc.v
+
 test: install
 	python3 setup.py test # could just run nosetest3...
 
diff --git a/src/soc/litex/florent/Makefile b/src/soc/litex/florent/Makefile
index d1c5cc1d..ab73b7bf 100644
--- a/src/soc/litex/florent/Makefile
+++ b/src/soc/litex/florent/Makefile
@@ -5,6 +5,7 @@ ls180:
 	cp build/ls180/gateware/mem_1.init .
 	cp build/ls180/gateware/mem_2.init .
 	cp build/ls180/gateware/mem_3.init .
+	cp build/ls180/gateware/mem_4.init .
 	cp libresoc/libresoc.v .
 	yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'
diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 55a84c97..189216e2 100644
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -187,6 +187,11 @@ class LibreSoC(CPU):
         if jtag_en:
             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
 
+        if "sram4k" in variant or variant == 'ls180':
+            self.srams = srams = []
+            for i in range(4):
+                srams.append(wb.Interface(data_width=64, adr_width=29))
+
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 
@@ -261,6 +266,10 @@ class LibreSoC(CPU):
             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
         if jtag_en:
             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
+        if "sram4k" in variant or variant == 'ls180':
+            for i, sram in enumerate(srams):
+                self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram))
+
         # and set ibus advanced tags to zero (disable)
         self.cpu_params['i_ibus__cti'] = 0
         self.cpu_params['i_ibus__bte'] = 0
diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 41979267..3224f6d1 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -321,9 +321,14 @@ class LibreSoCSim(SoCCore):
 
         self.mem_map["main_ram"] = 0x90000000
         self.mem_map["sram"] = 0x00000000
-        self.mem_map["sram1"] = 0x00001000
-        self.mem_map["sram2"] = 0x00002000
-        self.mem_map["sram3"] = 0x00003000
+        self.mem_map["sram1"] = 0x00000200
+        self.mem_map["sram2"] = 0x00000400
+        self.mem_map["sram3"] = 0x00000600
+        self.mem_map["sram4"] = 0x00000800
+        self.mem_map["sram4k_0"] = 0x00001000
+        self.mem_map["sram4k_1"] = 0x00002000
+        self.mem_map["sram4k_2"] = 0x00003000
+        self.mem_map["sram4k_3"] = 0x00004000
 
         # SoCCore -------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
@@ -349,10 +354,11 @@ class LibreSoCSim(SoCCore):
             )
         self.platform.name = "ls180"
 
-        # add 3 more 4k integrated SRAMs
+        # add 4 more 4k integrated SRAMs
         self.add_ram("sram1", self.mem_map["sram1"], 0x200)
         self.add_ram("sram2", self.mem_map["sram2"], 0x200)
         self.add_ram("sram3", self.mem_map["sram3"], 0x200)
+        self.add_ram("sram4", self.mem_map["sram4"], 0x200)
 
         # SDR SDRAM ----------------------------------------------
         if False: # not self.integrated_main_ram_size:
@@ -370,6 +376,13 @@ class LibreSoCSim(SoCCore):
             ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
             self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
 
+            # add 4x 4k SRAMs
+            for i, sram_wb in enumerate(self.cpu.srams):
+                name = 'sram4k_%d' % i
+                sram_adr = self.mem_map[name]
+                ics_region = SoCRegion(origin=sram_adr, size=0x1000)
+                self.bus.add_slave(name=name, slave=sram_wb, region=ics_region)
+
         # CRG -----------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"),
                                   platform.request("sys_rst"))