From: Cesar Strauss <cestrauss@gmail.com>
Date: Fri, 15 Apr 2022 19:36:05 +0000 (-0300)
Subject: Fix incorrect signal widths
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=11de641fb71cd6939d5f67d367865d6ac3f3220d

Fix incorrect signal widths

dbg_data is the width of a write lane (granularity) and dbg_wrote is a
single bit.
---

diff --git a/src/soc/regfile/sram_wrapper.py b/src/soc/regfile/sram_wrapper.py
index 5ce85b82..024563e6 100644
--- a/src/soc/regfile/sram_wrapper.py
+++ b/src/soc/regfile/sram_wrapper.py
@@ -258,8 +258,9 @@ class PhasedDualPortRegfile(Elaboratable):
         # debug signals, only used in formal proofs
         self.dbg_addr = Signal(addr_width); """debug: address under test"""
         self.dbg_we_mask = Signal(we_width); """debug: write lane under test"""
-        self.dbg_data = Signal(data_width); """debug: data to keep in sync"""
-        self.dbg_wrote = Signal(addr_width); """debug: data is valid"""
+        gran = self.data_width // self.we_width
+        self.dbg_data = Signal(gran); """debug: data to keep in sync"""
+        self.dbg_wrote = Signal(); """debug: data is valid"""
 
     def elaborate(self, platform):
         m = Module()