From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 29 Mar 2022 18:18:07 +0000 (+0100)
Subject: set clock freq Constant length to 32-bit in Tercel.
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=9e4e5fb690bf8a893c17f5f02ffbb6728f720eb8

set clock freq Constant length to 32-bit in Tercel.
this really needs to come from SYSCON
---

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index 1e204b5a..934fda20 100644
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -45,7 +45,7 @@ class Tercel(Elaboratable):
         # TODO, sort this out.
         assert clk_freq is not None
         clk_freq = round(clk_freq)
-        self.clk_freq = Const(clk_freq, clk_freq.bit_length())
+        self.clk_freq = Const(clk_freq, 32) #clk_freq.bit_length())
 
         # set up the wishbone busses
         if features is None: