From: Luke Kenneth Casson Leighton Date: Tue, 18 Jun 2019 08:26:25 +0000 (+0100) Subject: sort out go_ld_i and go_st_i X-Git-Tag: div_pipeline~1844 X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=a7b8337867b15252dc1c63b7e3dc757d3449a6e1 sort out go_ld_i and go_st_i --- diff --git a/src/experiment/alu_hier.py b/src/experiment/alu_hier.py index 8e3677a5..9659059c 100644 --- a/src/experiment/alu_hier.py +++ b/src/experiment/alu_hier.py @@ -104,9 +104,9 @@ class ALU(Elaboratable): m.d.sync += self.counter.eq(7) with m.Elif(self.op == 1): # SUB to take 1, straight away m.d.sync += self.counter.eq(1) + m.d.comb += go_now.eq(1) with m.Else(): # ADD to take 2 m.d.sync += self.counter.eq(2) - m.d.comb += go_now.eq(1) with m.Else(): # input says no longer valid, so drop ready as well. # a "proper" ALU would have had to sync in the opcode and a/b ops diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py index 8b66da4b..0a0a4c2e 100644 --- a/src/experiment/compldst.py +++ b/src/experiment/compldst.py @@ -78,8 +78,12 @@ class LDSTCompUnit(Elaboratable): self.sto_rel_o = Signal(reset_less=True) # request store (to mem) self.req_rel_o = Signal(reset_less=True) # request write (result) self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU) + + # hmm... TODO... move these to outside of LDSTCompUnit self.load_mem_o = Signal(reset_less=True) # activate memory LOAD self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE + self.ld_o = Signal(reset_less=True) # operation is a LD + self.st_o = Signal(reset_less=True) # operation is a ST def elaborate(self, platform): m = Module() @@ -149,7 +153,7 @@ class LDSTCompUnit(Elaboratable): busy_o = self.busy_o comb += self.busy_o.eq(opc_l.q) # busy out comb += self.rd_rel_o.eq(src_l.q & busy_o) # src1/src2 req rel - comb += self.sto_rel_o.eq(sto_l.q & busy_o & self.shadown_i) + comb += self.sto_rel_o.eq(sto_l.q & busy_o & self.shadown_i & op_is_st) # request release enabled based on if op is a LD/ST or a plain ALU # if op is an ADD/SUB or a LD, req_rel activates. @@ -199,6 +203,8 @@ class LDSTCompUnit(Elaboratable): comb += op_ldst.eq(op_is_ld | op_is_st) comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i) comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i) + comb += self.ld_o.eq(op_is_ld) + comb += self.st_o.eq(op_is_st) # on a go_read, tell the ALU we're accepting data. # NOTE: this spells TROUBLE if the ALU isn't ready! diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 94d59f4d..05de08fa 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -121,6 +121,8 @@ class CompUnitsBase(Elaboratable): self.rd_rel_o = Signal(n_units, reset_less=True) self.req_rel_o = Signal(n_units, reset_less=True) if ldstmode: + self.ld_o = Signal(n_units, reset_less=True) # op is LD + self.st_o = Signal(n_units, reset_less=True) # op is ST self.adr_rel_o = Signal(n_units, reset_less=True) self.sto_rel_o = Signal(n_units, reset_less=True) self.req_rel_o = Signal(n_units, reset_less=True) @@ -185,9 +187,13 @@ class CompUnitsBase(Elaboratable): stmem_l = [] go_ad_l = [] go_st_l = [] + ld_l = [] + st_l = [] adr_rel_l = [] sto_rel_l = [] for alu in self.units: + ld_l.append(alu.ld_o) + st_l.append(alu.st_o) adr_rel_l.append(alu.adr_rel_o) sto_rel_l.append(alu.sto_rel_o) ldmem_l.append(alu.load_mem_o) @@ -568,11 +574,16 @@ class Scoreboard(Elaboratable): # connect loadable / storable to go_ld/go_st. # XXX should only be done when the memory ld/st has actually happened! - - comb += memfus.go_ld_i.eq(memfus.loadable_o & memfus.addr_nomatch_o) - comb += memfus.go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o) + go_st_i = Signal(cul.n_units, reset_less=True) + go_ld_i = Signal(cul.n_units, reset_less=True) + comb += go_ld_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\ + cul.req_rel_o & cul.ld_o) + comb += go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\ + cul.sto_rel_o & cul.st_o) + comb += memfus.go_ld_i.eq(go_ld_i) + comb += memfus.go_st_i.eq(go_st_i) #comb += cul.go_wr_i.eq(memfus.loadable_o & memfus.addr_nomatch_o) - comb += cul.go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o) + comb += cul.go_st_i.eq(go_st_i) #comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus]) #comb += cu.go_wr_i[0:n_intfus].eq(go_wr_o[0:n_intfus]) @@ -1139,7 +1150,7 @@ def scoreboard_sim(dut, alusim): if True: # LD/ST test (with immediate) instrs.append( (1, 2, 2, 0x10, 1, 1, (0, 0)) ) - #instrs.append( (1, 2, 7, 0x10, 1, 1, (0, 0)) ) + instrs.append( (1, 2, 7, 0x12, 1, 1, (0, 0)) ) if False: instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )