From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 10 Jun 2019 10:34:14 +0000 (+0100)
Subject: starting to run into things being broken in LD/ST Comp (yay)
X-Git-Tag: div_pipeline~1855
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=cdfffd55cf53cd4a18ffadedb927129393abf089

starting to run into things being broken in LD/ST Comp (yay)
---

diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py
index 3e2d379e..88d49647 100644
--- a/src/experiment/compldst.py
+++ b/src/experiment/compldst.py
@@ -52,6 +52,7 @@ class LDSTCompUnit(Elaboratable):
         * :go_die_i:   resets the unit back to "wait for issue"
     """
     def __init__(self, rwid, opwid, alu, mem):
+        self.opwid = opwid
         self.rwid = rwid
         self.alu = alu
         self.mem = mem
@@ -113,14 +114,6 @@ class LDSTCompUnit(Elaboratable):
         op_ldst = Signal(reset_less=True)
         op_is_imm = Signal(reset_less=True)
 
-        comb += op_alu.eq(self.oper_i[0])
-        comb += op_is_imm.eq(self.oper_i[1])
-        comb += op_is_ld.eq(self.oper_i[2])
-        comb += op_is_st.eq(self.oper_i[3])
-        comb += op_ldst.eq(op_is_ld | op_is_st)
-        comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
-        comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
-
         # select immediate or src2 reg to add
         src2_or_imm = Signal(self.rwid, reset_less=True)
         src_sel = Signal(reset_less=True)
@@ -189,13 +182,24 @@ class LDSTCompUnit(Elaboratable):
         latchregister(m, src2_or_imm, self.alu.b, src_sel)
 
         # create a latch/register for the operand
+        oper_r = Signal(self.opwid, reset_less=True) # Dest register
+        latchregister(m, self.oper_i, oper_r, self.issue_i)
         alu_op = Cat(op_alu, 0, op_is_imm) # using alu_hier, here.
-        latchregister(m, alu_op, self.alu.op, self.issue_i)
+        comb += self.alu.op.eq(alu_op)
 
         # and one for the output from the ALU
         data_r = Signal(self.rwid, reset_less=True) # Dest register
         latchregister(m, self.alu.o, data_r, req_l.q)
 
+        # decode bits of operand (latched)
+        comb += op_alu.eq(oper_r[0])
+        comb += op_is_imm.eq(oper_r[1])
+        comb += op_is_ld.eq(oper_r[2])
+        comb += op_is_st.eq(oper_r[3])
+        comb += op_ldst.eq(op_is_ld | op_is_st)
+        comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
+        comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
+
         with m.If(self.go_wr_i):
             comb += self.data_o.eq(data_r)
 
diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 5d67c05b..ccb26c1c 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -202,7 +202,7 @@ class CompUnitsBase(Elaboratable):
 
 class CompUnitLDSTs(CompUnitsBase):
 
-    def __init__(self, rwid, opwid, mem):
+    def __init__(self, rwid, opwid, n_ldsts, mem):
         """ Inputs:
 
             * :rwid:   bit width of register file(s) - both FP and INT
@@ -215,11 +215,12 @@ class CompUnitLDSTs(CompUnitsBase):
         self.imm_i = Signal(rwid, reset_less=True)
 
         # Int ALUs
-        add1 = ALU(rwid)
-        add2 = ALU(rwid)
+        alus = []
+        for i in range(n_ldsts):
+            alus.append(ALU(rwid))
 
         units = []
-        for alu in [add1, add2]:
+        for alu in alus:
             aluopwid = 4 # see compldst.py for "internal" opcode
             units.append(LDSTCompUnit(rwid, aluopwid, alu, mem))
 
@@ -402,8 +403,8 @@ class Scoreboard(Elaboratable):
 
         # issue q needs to get at these
         self.aluissue = IssueUnitGroup(2)
+        self.lsissue = IssueUnitGroup(2)
         self.brissue = IssueUnitGroup(1)
-        self.lsissue = IssueUnitGroup(1)
         # and these
         self.alu_oper_i = Signal(4, reset_less=True)
         self.alu_imm_i = Signal(rwid, reset_less=True)
@@ -454,10 +455,10 @@ class Scoreboard(Elaboratable):
 
         # LDST Comp Units
         n_ldsts = 2
-        cul = CompUnitLDSTs(self.rwid, 4, None)
+        cul = CompUnitLDSTs(self.rwid, 4, self.lsissue.n_insns, None)
 
         # Comp Units
-        m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub, cul])
+        m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cul, cub])
         bgt = cub.bgt # get at the branch computation unit
         br1 = cub.br1
 
@@ -478,7 +479,7 @@ class Scoreboard(Elaboratable):
         # INT/FP Issue Unit
         regdecode = RegDecode(self.n_regs)
         m.submodules.regdecode = regdecode
-        issueunit = IssueUnitArray([self.aluissue, self.brissue, self.lsissue])
+        issueunit = IssueUnitArray([self.aluissue, self.lsissue, self.brissue])
         m.submodules.issueunit = issueunit
 
         # Shadow Matrix.  currently n_intfus shadows, to be used for
@@ -1089,10 +1090,10 @@ def scoreboard_sim(dut, alusim):
 
         # create some instructions (some random, some regression tests)
         instrs = []
-        if True:
+        if False:
             instrs = create_random_ops(dut, 15, True, 4)
 
-        if False: # LD test (with immediate)
+        if True: # LD test (with immediate)
             instrs.append( (1, 2, 2, 0x10, 1, 20, (0, 0)) )
 
         if False: