From 1d3441ee494729433c8f5f18924c0f60f68374af Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 18 Feb 2022 19:41:42 +0000 Subject: [PATCH] couple of adjustments to reduce gate count in i/d-cache --- src/soc/experiment/dcache.py | 13 ++++++++----- src/soc/experiment/icache.py | 8 +++++--- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 0b74c4cd..04c222fa 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1619,11 +1619,15 @@ class DCache(Elaboratable, DCacheConfig): # Compare the whole address in case the # request in r1.req is not the one that # started this refill. + rowmatch = Signal() + lastrow = Signal() + comb += rowmatch.eq(r1.store_row == + self.get_row(r1.req.real_addr)) + comb += lastrow.eq(self.is_last_row(r1.store_row, + r1.end_row_ix)) with m.If(r1.full & r1.req.same_tag & ((r1.dcbz & req.dcbz) | - (r1.req.op == Op.OP_LOAD_MISS)) & - (r1.store_row == - self.get_row(r1.req.real_addr))): + (r1.req.op == Op.OP_LOAD_MISS)) & rowmatch): sync += r1.full.eq(r1_next_cycle) sync += r1.slow_valid.eq(1) with m.If(r1.mmu_req): @@ -1634,8 +1638,7 @@ class DCache(Elaboratable, DCacheConfig): sync += r1.use_forward1.eq(1) # Check for completion - with m.If(ld_stbs_done & self.is_last_row(r1.store_row, - r1.end_row_ix)): + with m.If(ld_stbs_done & lastrow): # Complete wishbone cycle sync += r1.wb.cyc.eq(0) diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 9e63f9ac..4329fd5b 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -524,9 +524,11 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig): # Test if pending request is a hit on any way hitcond = Signal() - comb += hitcond.eq((r.state == State.WAIT_ACK) - & (req_index == r.store_index) - & r.rows_valid[req_row % self.ROW_PER_LINE] + rowvalid = Signal() + comb += rowvalid.eq(r.rows_valid[req_row % self.ROW_PER_LINE]) + comb += hitcond.eq((r.state == State.WAIT_ACK) & + (req_index == r.store_index) & + rowvalid ) # i_in.req asserts Decoder active cvb = Signal(self.NUM_WAYS) -- 2.30.2