From 20fcdd7b7dbccd5512a683e2bbcf318f8e084250 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 12 Mar 2022 16:08:29 +0000 Subject: [PATCH] add extra pipeline stages to ALU FU to make timing --- src/soc/fu/alu/pipeline.py | 40 ++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/src/soc/fu/alu/pipeline.py b/src/soc/fu/alu/pipeline.py index a9c4f337..baaf69c2 100644 --- a/src/soc/fu/alu/pipeline.py +++ b/src/soc/fu/alu/pipeline.py @@ -5,52 +5,58 @@ from soc.fu.alu.main_stage import ALUMainStage from soc.fu.alu.output_stage import ALUOutputStage -class ALUStagesOld(PipeModBaseChain): +class ALUStages(PipeModBaseChain): def get_chain(self): inp = ALUInputStage(self.pspec) main = ALUMainStage(self.pspec) - return [inp, main, out] - - -class ALUStageEnd(PipeModBaseChain): - def get_chain(self): out = ALUOutputStage(self.pspec) - return [out] + return [inp, main, out] -class ALUBasePipeOld(ControlBase): +class ALUBasePipe(ControlBase): def __init__(self, pspec): ControlBase.__init__(self) self.pspec = pspec self.pipe1 = ALUStages(pspec) - self.pipe2 = ALUStageEnd(pspec) - self._eqs = self.connect([self.pipe1, self.pipe2]) + self._eqs = self.connect([self.pipe1]) def elaborate(self, platform): m = ControlBase.elaborate(self, platform) m.submodules.pipe1 = self.pipe1 - m.submodules.pipe2 = self.pipe2 m.d.comb += self._eqs return m - -class ALUStages(PipeModBaseChain): +class ALUStages1(PipeModBaseChain): def get_chain(self): inp = ALUInputStage(self.pspec) + return [inp] + +class ALUStages2(PipeModBaseChain): + def get_chain(self): main = ALUMainStage(self.pspec) + return [main] + + +class ALUStages3(PipeModBaseChain): + def get_chain(self): out = ALUOutputStage(self.pspec) - return [inp, main, out] + return [out] class ALUBasePipe(ControlBase): def __init__(self, pspec): ControlBase.__init__(self) self.pspec = pspec - self.pipe1 = ALUStages(pspec) - self._eqs = self.connect([self.pipe1]) + self.pipe1 = ALUStages1(pspec) + self.pipe2 = ALUStages2(pspec) + self.pipe3 = ALUStages3(pspec) + self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3]) def elaborate(self, platform): m = ControlBase.elaborate(self, platform) - m.submodules.pipe1 = self.pipe1 + m.submodules.logical_pipe1 = self.pipe1 + m.submodules.logical_pipe2 = self.pipe2 + m.submodules.logical_pipe3 = self.pipe3 m.d.comb += self._eqs return m + -- 2.30.2