From 226a07488e2c87d3b1b26e65ea7a9294b685881c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 7 Jun 2019 23:20:12 +0100 Subject: [PATCH] rename v_rd_rsel_o in dependence cell as well --- src/scoreboard/dependence_cell.py | 8 ++++---- src/scoreboard/fu_reg_matrix.py | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index 1a8f588b..65c333c5 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -35,8 +35,8 @@ class DependencyRow(Elaboratable): self.rd_pend_i = Signal(n_reg, reset_less=True) # Read pend in (top) self.wr_pend_i = Signal(n_reg, reset_less=True) # Write pend in (top) - self.rd_rsel_o = Signal(n_reg, reset_less=True) # Read pend out (bot) - self.wr_rsel_o = Signal(n_reg, reset_less=True) # Write pend out (bot) + self.v_rd_rsel_o = Signal(n_reg, reset_less=True) # Read pend out (bot) + self.v_wr_rsel_o = Signal(n_reg, reset_less=True) # Write pend out (bot) self.go_wr_i = Signal(reset_less=True) # Go Write in (left) self.go_rd_i = Signal(reset_less=True) # Go Read in (left) @@ -87,8 +87,8 @@ class DependencyRow(Elaboratable): # to be accumulated to indicate if register is in use (globally) # after ORing, is fed back in to rd_pend_i / wr_pend_i - m.d.comb += self.rd_rsel_o.eq(src1_c.qlq | src2_c.qlq) - m.d.comb += self.wr_rsel_o.eq(dest_c.qlq) + m.d.comb += self.v_rd_rsel_o.eq(src1_c.qlq | src2_c.qlq) + m.d.comb += self.v_wr_rsel_o.eq(dest_c.qlq) return m diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py index 90ff219d..a578a996 100644 --- a/src/scoreboard/fu_reg_matrix.py +++ b/src/scoreboard/fu_reg_matrix.py @@ -166,8 +166,8 @@ class FURegDepMatrix(Elaboratable): wr_pend_v = [] for fu in range(self.n_fu_row): dc = dm[fu] - rd_pend_v.append(dc.rd_rsel_o) - wr_pend_v.append(dc.wr_rsel_o) + rd_pend_v.append(dc.v_rd_rsel_o) + wr_pend_v.append(dc.v_wr_rsel_o) rd_v = GlobalPending(self.n_reg_col, rd_pend_v) wr_v = GlobalPending(self.n_reg_col, wr_pend_v) m.submodules.rd_v = rd_v -- 2.30.2