From 31f03f4ba054d913570fbea5dc157c2776053046 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 27 Feb 2022 18:01:54 +0000 Subject: [PATCH] use XLEN in Function Units (starting with ALU) --- src/soc/fu/alu/main_stage.py | 25 +++++++++++++------------ src/soc/fu/common_output_stage.py | 2 +- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py index f4ad4918..4704e4ff 100644 --- a/src/soc/fu/alu/main_stage.py +++ b/src/soc/fu/alu/main_stage.py @@ -38,6 +38,7 @@ class ALUMainStage(PipeModBase): return ALUOutputData(self.pspec) # defines pipeline stage output format def elaborate(self, platform): + XLEN = self.pspec.XLEN m = Module() comb = m.d.comb @@ -69,11 +70,11 @@ class ALUMainStage(PipeModBase): comb += b_i.eq(b) # into trap pipeline with m.Elif(is_32bit): with m.If(op.is_signed): - comb += a_i.eq(exts(a, 32, 64)) - comb += b_i.eq(exts(b, 32, 64)) + comb += a_i.eq(exts(a, 32, XLEN)) + comb += b_i.eq(exts(b, 32, XLEN)) with m.Else(): - comb += a_i.eq(extz(a, 32, 64)) - comb += b_i.eq(extz(b, 32, 64)) + comb += a_i.eq(extz(a, 32, XLEN)) + comb += b_i.eq(extz(b, 32, XLEN)) with m.Else(): comb += a_i.eq(a) comb += b_i.eq(b) @@ -94,7 +95,7 @@ class ALUMainStage(PipeModBase): #### CMP, CMPL v3.0B p85-86 with m.Case(MicrOp.OP_CMP): - a_n = Signal(64) # temporary - inverted a + a_n = Signal(XLEN) # temporary - inverted a tval = Signal(5) a_lt = Signal() carry_32 = Signal() @@ -108,17 +109,17 @@ class ALUMainStage(PipeModBase): # this is supposed to be inverted (b-a, not a-b) comb += a_n.eq(~a) # sigh a gets inverted comb += carry_32.eq(add_o[33] ^ a[32] ^ b[32]) - comb += carry_64.eq(add_o[65]) + comb += carry_64.eq(add_o[XLEN+1]) comb += zerolo.eq(~((a_n[0:32] ^ b[0:32]).bool())) - comb += zerohi.eq(~((a_n[32:64] ^ b[32:64]).bool())) + comb += zerohi.eq(~((a_n[32:XLEN] ^ b[32:XLEN]).bool())) with m.If(zerolo & (is_32bit | zerohi)): # values are equal comb += tval[2].eq(1) with m.Else(): - comb += msb_a.eq(Mux(is_32bit, a_n[31], a_n[63])) - comb += msb_b.eq(Mux(is_32bit, b[31], b[63])) + comb += msb_a.eq(Mux(is_32bit, a_n[31], a_n[XLEN-1])) + comb += msb_b.eq(Mux(is_32bit, b[31], b[XLEN-1])) C0 = Const(0, 1) with m.If(msb_a != msb_b): # Subtraction might overflow, but @@ -164,11 +165,11 @@ class ALUMainStage(PipeModBase): with m.Case(MicrOp.OP_EXTS): with m.If(op.data_len == 1): - comb += o.data.eq(exts(a, 8, 64)) + comb += o.data.eq(exts(a, 8, XLEN)) with m.If(op.data_len == 2): - comb += o.data.eq(exts(a, 16, 64)) + comb += o.data.eq(exts(a, 16, XLEN)) with m.If(op.data_len == 4): - comb += o.data.eq(exts(a, 32, 64)) + comb += o.data.eq(exts(a, 32, XLEN)) comb += o.ok.eq(1) # output register ################### diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 45106984..c4f085fd 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -49,7 +49,7 @@ class CommonOutputStage(PipeModBase): # XXX ah. right. this needs to be done only if the *mode* is 32-bit # (an MSR bit) # see https://bugs.libre-soc.org/show_bug.cgi?id=424 - target = Signal(64, reset_less=True) + target = Signal.like(o) #with m.If(op.is_32bit): # comb += target.eq(o[:32]) #with m.Else(): -- 2.30.2