From 348b371b5084f0eda168b31aefb9088a2c24a1ae Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 18 Feb 2022 20:49:36 +0000 Subject: [PATCH] use block_ram attribute for FPGA synthesis --- src/soc/experiment/cache_ram.py | 3 ++- src/soc/experiment/dcache.py | 14 +++++++++----- src/soc/experiment/icache.py | 8 ++++++-- 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py index a79b6872..784b9a81 100644 --- a/src/soc/experiment/cache_ram.py +++ b/src/soc/experiment/cache_ram.py @@ -32,7 +32,8 @@ class CacheRam(Elaboratable): # set up the Cache RAM Memory and create one read and one write port # the read port is *not* transparent (does not pass write-thru-read) #attribute ram_style of ram : signal is "block"; - ram = Memory(depth=SIZE, width=WIDTH) + ram = Memory(depth=SIZE, width=WIDTH, + attrs={'syn_ramstyle': "block_ram"}) m.submodules.rdport = rdport = ram.read_port(transparent=False) m.submodules.wrport = wrport = ram.write_port(granularity=8) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 3b67b7cf..ce1967bd 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -513,12 +513,14 @@ class DTLBUpdate(Elaboratable): print (" TLB_NUM_WAYS", cfg.TLB_NUM_WAYS) # TAG and PTE Memory SRAMs. transparent, write-enables are TLB_NUM_WAYS - tagway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_TAG_WAY_BITS) + tagway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_TAG_WAY_BITS, + attrs={'syn_ramstyle': "block_ram"}) m.submodules.rd_tagway = rd_tagway = tagway.read_port() m.submodules.wr_tagway = wr_tagway = tagway.write_port( granularity=cfg.TLB_EA_TAG_BITS) - pteway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_PTE_WAY_BITS) + pteway = Memory(depth=cfg.TLB_SET_SIZE, width=cfg.TLB_PTE_WAY_BITS, + attrs={'syn_ramstyle': "block_ram"}) m.submodules.rd_pteway = rd_pteway = pteway.read_port() m.submodules.wr_pteway = wr_pteway = pteway.write_port( granularity=cfg.TLB_PTE_BITS) @@ -966,8 +968,9 @@ class DCache(Elaboratable, DCacheConfig): m_in, d_in = self.m_in, self.d_in - # synchronous tag read-port - m.submodules.rd_tag = rd_tag = self.tagmem.read_port() + # synchronous tag read-port: NOT TRANSPARENT (cannot pass through + # write-to-a-read at the same time), seems to pass tests ok + m.submodules.rd_tag = rd_tag = self.tagmem.read_port(transparent=False) index = Signal(self.INDEX_BITS) @@ -1757,7 +1760,8 @@ class DCache(Elaboratable, DCacheConfig): cache_valids = self.CacheValidsArray() cache_tag_set = Signal(self.TAG_RAM_WIDTH) - self.tagmem = Memory(depth=self.NUM_LINES, width=self.TAG_RAM_WIDTH) + self.tagmem = Memory(depth=self.NUM_LINES, width=self.TAG_RAM_WIDTH, + attrs={'syn_ramstyle': "block_ram"}) """note: these are passed to nmigen.hdl.Memory as "attributes". don't know how, just that they are. diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 4329fd5b..8e457be5 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -865,9 +865,13 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig): replace_way = Signal(self.WAY_BITS) self.tlbmem = Memory(depth=self.TLB_SIZE, - width=self.TLB_EA_TAG_BITS+self.TLB_PTE_BITS) + width=self.TLB_EA_TAG_BITS+self.TLB_PTE_BITS, + #attrs={'syn_ramstyle': "block_ram"} + ) self.tagmem = Memory(depth=self.NUM_LINES, - width=self.TAG_RAM_WIDTH) + width=self.TAG_RAM_WIDTH, + #attrs={'syn_ramstyle': "block_ram"} + ) # call sub-functions putting everything together, # using shared signals established above -- 2.30.2