From 3d5d183cda1cbc4697a87697dbd7ab6e8a04765b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 4 Jul 2022 16:12:46 +0100 Subject: [PATCH] add signal for resetting trap internal state (kaivb cache) --- src/soc/fu/trap/main_stage.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 2498cfd1..8127e226 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -59,6 +59,7 @@ class TrapMainStage(PipeModBase): self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn]) self.fields.create_specs() self.kaivb = Signal(64) # KAIVB SPR + self.state_reset = Signal() # raise high to reset KAIVB cache def trap(self, m, trap_addr, return_addr): """trap. sets new PC, stores MSR and old PC in SRR1 and SRR0 @@ -153,6 +154,10 @@ class TrapMainStage(PipeModBase): srr0_o, srr1_o, svsrr0_o = self.o.srr0, self.o.srr1, self.o.svsrr0 traptype, trapaddr = op.traptype, op.trapaddr + # hard reset of KAIVB + with m.If(self.state_reset): + sync += self.kaivb.eq(0) + # take copy of D-Form TO field i_fields = self.fields.FormD to = Signal(i_fields.TO[0:-1].shape()) -- 2.30.2