From 5d496a6b50ec3b9e00586e777651c60a1921688d Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sun, 5 Apr 2020 19:28:12 -0400 Subject: [PATCH] Auto insert instruction fields into the namespace --- src/soc/decoder/isa/caller.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 2199d731..39d99d5e 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -129,15 +129,17 @@ class ISACaller: # from spec # then "yield" fields only from op_fields rather than hard-coded # list, here. - for name in ['SI', 'UI', 'D', 'BD']: - signal = getattr(self.decoder, name) - val = yield signal - self.namespace[name] = SelectableInt(val, bits=signal.width) + fields = self.decoder.sigforms[formname] + for name in fields._fields: + if name not in ["RA", "RB", "RT"]: + sig = getattr(fields, name) + val = yield sig + self.namespace[name] = SelectableInt(val, sig.width) def call(self, name): # TODO, asmregs is from the spec, e.g. add RT,RA,RB # see http://bugs.libre-riscv.org/show_bug.cgi?id=282 - fn, read_regs, uninit_regs, write_regs, op_fields, asmregs, form \ + fn, read_regs, uninit_regs, write_regs, op_fields, form, asmregs \ = self.instrs[name] yield from self.prep_namespace(form, op_fields) -- 2.30.2