From 91abb3c8fd89ccac2341ce04ae14278a4ab1caaa Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Apr 2022 14:13:23 +0100
Subject: [PATCH] add option Spec to XICS ICP/ICS to be able to activate (in a
 horrible hack way) make_wb_layout to add stall this is done by spotting
 "spec.microwatt_compat" adds stall blegh

---
 src/soc/interrupts/xics.py | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py
index d1bc0296..a5ed8f0d 100644
--- a/src/soc/interrupts/xics.py
+++ b/src/soc/interrupts/xics.py
@@ -75,9 +75,10 @@ def bswap(v):
 
 class XICS_ICP(Elaboratable):
 
-    def __init__(self):
-        class Spec: pass
-        spec = Spec()
+    def __init__(self, spec=None):
+        if spec is None:
+            class Spec: pass
+            spec = Spec()
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = 32
@@ -226,12 +227,13 @@ class Xive(RecordObject):
 
 
 class XICS_ICS(Elaboratable):
-    def __init__(self, SRC_NUM=16, PRIO_BITS=8):
+    def __init__(self, spec=None, SRC_NUM=16, PRIO_BITS=8):
         self.SRC_NUM = SRC_NUM
         self.PRIO_BITS = PRIO_BITS
         self.pri_masked = (1<<self.PRIO_BITS)-1
-        class Spec: pass
-        spec = Spec()
+        if spec is None:
+            class Spec: pass
+            spec = Spec()
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = 32
-- 
2.30.2